AT45DB642D-CNU Atmel, AT45DB642D-CNU Datasheet - Page 12

• Manufacturer Part Number: AT45DB642D-CNU
• Description: IC FLASH 64MBIT 66MHZ 8CASON
• Manufacturer: Atmel

Specifications of AT45DB642D-CNU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 64M (8192 pages x 1056 bytes)
• Speed: 66MHz
• Interface: Parallel/Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-CASON
• Package: 8CASON
• Density: 64 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 256KByte x 32
• Timing Type: Synchronous
• Interface Type: Parallel|Serial-SPI
• Data Bus Width: 8 bit
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 15 mA
• Mounting Style: SMD/SMT
• Organization: 256 KB x 32
• Ic Interface Type: Parallel, Serial
• Clock Frequency: 66MHz
• Supply Voltage Range: 2.7V To 3.6V
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.8
8. Sector Protection
12
Main Memory Page Program Through Buffer
AT45DB642D
The WP pin can be asserted while the device is erasing, but protection will not be activated until
the internal erase cycle completes.
Figure 7-1.
Note:
This operation is a combination of the Buffer Write and Buffer to Main Memory Page Program
with Built-in Erase operations. Data is first clocked into buffer 1 or buffer 2 from the input pins (SI
or I/O7-I/O0) and then programmed into a specified page in the main memory. To perform the
main memory page program through buffer for the standard DataFlash page size (1056 bytes), a
1-byte opcode, 82H for buffer 1 or 85H for buffer 2, must first be clocked into the device, fol-
lowed by three address bytes. The address bytes are comprised of 13 page address bits,
(PA12-PA0) that select the page in the main memory where data is to be written, and 11 buffer
address bits (BFA10-BFA0) that select the first byte in the buffer to be written. To perform a
main memory page program through buffer for the binary page size (1024 bytes), the opcode
82H for buffer 1 or 85H for buffer 2, must be clocked into the device followed by three address
bytes consisting of 13 page address bits (A22 - A10) that specify the page in the main memory
to be written, and 10 buffer address bits (BFA9 - BFA0) that selects the first byte in the buffer to
be written. After all address bytes are clocked in, the part will take data from the input pins and
store it in the specified data buffer. If the end of the buffer is reached, the device will wrap
around back to the beginning of the buffer. When there is a low-to-high transition on the CS pin,
the part will first erase the selected page in main memory to all 1s and then program the data
stored in the buffer into that memory page. Both the erase and the programming of the page are
internally self-timed and should take place in a maximum time of t
register and the RDY/BUSY pin will indicate that the part is busy.
Two protection methods, hardware and software controlled, are provided for protection against
inadvertent or erroneous program and erase cycles. The software controlled method relies on
the use of software commands to enable and disable sector protection while the hardware con-
trolled method employs the use of the Write Protect (WP) pin. The selection of which sectors
that are to be protected or unprotected against program and erase operations is specified in the
nonvolatile Sector Protection Register. The status of whether or not sector protection has been
enabled or disabled by either the software or the hardware controlled methods can be deter-
mined by checking the Status Register.
Command
Chip Erase
1. Refer to the errata regarding Chip Erase on
Chip Erase
CS
SI
Each transition
represents 8 bits
Opcode
Byte 1
Opcode
Byte 1
Byte 2
C7H
page
Opcode
Byte 3
57.
Byte 2
94H
Opcode
Byte 4
EP
. During this time, the status
Byte 3
80H
3542K–DFLASH–04/09
Byte 4
9AH