AT45DB642D-CNU Atmel, AT45DB642D-CNU Datasheet - Page 8

• Manufacturer Part Number: AT45DB642D-CNU
• Description: IC FLASH 64MBIT 66MHZ 8CASON
• Manufacturer: Atmel

Specifications of AT45DB642D-CNU

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 64M (8192 pages x 1056 bytes)
• Speed: 66MHz
• Interface: Parallel/Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-CASON
• Package: 8CASON
• Density: 64 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 256KByte x 32
• Timing Type: Synchronous
• Interface Type: Parallel|Serial-SPI
• Data Bus Width: 8 bit
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 15 mA
• Mounting Style: SMD/SMT
• Organization: 256 KB x 32
• Ic Interface Type: Parallel, Serial
• Clock Frequency: 66MHz
• Supply Voltage Range: 2.7V To 3.6V
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.4
6.5
8
Main Memory Page Read
Buffer Read
AT45DB642D
The CS pin must remain low during the loading of the opcode, the address bytes, and the read-
ing of data. When the end of a page in the main memory is reached during a Continuous Array
Read, the device will continue reading at the beginning of the next page with no delays incurred
during the page boundary crossover (the crossover from the end of one page to the beginning of
the next page). When the last bit in the main memory array has been read, the device will con-
tinue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the
beginning of the array. A low-to-high transition on the CS pin will terminate the read operation
and tri-state the output pin (SO). The Continuous Array Read bypasses both data buffers and
leaves the contents of the buffers unchanged.
A main memory page read allows the user to read data directly from any one of the 8,192 pages
in the main memory, bypassing both of the data buffers and leaving the contents of the buffers
unchanged. To start a page read from the standard DataFlash page size (1056 bytes), an
opcode of D2H must be clocked into the device followed by three address bytes (which comprise
the 24-bit page and byte address sequence) and a series of don’t care bytes (4 bytes if using the
serial interface or 19 bytes if using the 8-bit interface). The first 13 bits (PA12 - PA0) of the 24-bit
address sequence specify the page in main memory to be read, and the last 11 bits (BA10 -
a page read from the binary page size (1024 bytes), the opcode D2H must be clocked into the
device followed by three address bytes and a series of don’t care bytes (4 bytes if using the
serial interface or 19 bytes if using the 8-bit interface). The first 13 bits (A22 - A10) of the 24-bits
sequence specify which page of the main memory array to read, and the last 10 bits (A9 - A0) of
the 24-bits address sequence specify the starting byte address within the page. The don’t care
bytes that follow the address bytes are sent to initialize the read operation. Following the don’t
care bytes, additional pulses on SCK/CLK result in data being output on either the SO (serial
output) pin or the eight output pins (I/O7 - I/O0). The CS pin must remain low during the loading
of the opcode, the address bytes, the don’t care bytes, and the reading of data. When the end of
a page in main memory is reached, the device will continue reading back at the beginning of the
same page. A low-to-high transition on the CS pin will terminate the read operation and tri-state
the output pins (SO or I/O7 - I/O0). The maximum SCK/CLK frequency allowable for the Main
Memory Page Read is defined by the f
both data buffers and leaves the contents of the buffers unchanged.
The SRAM data buffers can be accessed independently from the main memory array, and utiliz-
ing the Buffer Read Command allows data to be sequentially read directly from the buffers. In
serial mode, four opcodes, D4H or D1H for buffer 1 and D6H or D3H for buffer 2 can be used for
the Buffer Read Command. The use of each opcode depends on the maximum SCK frequency
that will be used to read data from the buffer. The D4H and D6H opcode can be used at any
SCK frequency up to the maximum specified by f
for lower frequency read operations up to the maximum specified by f
In 8-bit mode, two opcodes, 54H for buffer 1 and 56H for buffer 2 can be used for the Buffer
Read Command. The two opcodes, 54H and 56H, can be used at any SCK frequency up to the
maximum specified by f
bytes), the opcode must be clocked into the device followed by three address bytes comprised
of 13 don’t care bits and 11 buffer address bits (BFA10 - BFA0). To perform a buffer read from
the binary buffer (1024 bytes), the opcode must be clocked into the device followed by three
address bytes comprised of 14 don’t care bits and 10 buffer address bits (BFA9 - BFA0).
BA0) of the 24-bit address sequence specify the starting byte address within that page. To start
CAR1
. To perform a buffer read from the standard DataFlash buffer (1056
SCK
specification. The Main Memory Page Read bypasses
CAR1
. The D1H and D3H opcode can be used
CAR2
.
3542K–DFLASH–04/09