MT45W4MW16BFB-708 WT TR Micron Technology Inc, MT45W4MW16BFB-708 WT TR Datasheet - Page 16

• Manufacturer Part Number: MT45W4MW16BFB-708 WT TR
• Description: IC PSRAM 64MBIT 70NS 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W4MW16BFB-708 WT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 64M (4M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Low-Power Operation
Standby Mode Operation
Temperature-Compensated Refresh
Partial-Array Refresh
Deep Power-Down Operation
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
During standby, the device current consumption is reduced to the level necessary to per-
form the DRAM refresh operation. Standby operation occurs when CE# is HIGH.
The device will enter a reduced power state upon completion of a READ or WRITE oper-
ation, or when the address and control inputs remain static for an extended period of
time. This mode will continue until a change occurs to the address or control inputs.
Temperature-compensated refresh (TCR) is used to adjust the refresh rate depending on
the device operating temperature. DRAM technology requires increasingly frequent
REFRESH operations to maintain data integrity as temperatures increase. More frequent
refresh is required due to increased leakage of the DRAM capacitive storage elements as
temperatures rise. A decreased refresh rate at lower temperatures will facilitate a savings
in standby current.
TCR allows for adequate refresh at four different temperature thresholds (+15°C, +45°C,
+70°C, and +85°C). The setting selected must be for a temperature higher than the case
temperature of the CellularRAM device. For example, if the case temperature is +50°C,
the system can minimize self refresh current consumption by selecting the +70°C set-
ting. The +15°C and +45°C settings would result in inadequate refreshing and cause data
corruption.
Partial-array refresh (PAR) restricts refresh operation to a portion of the total memory
array. This feature enables the device to reduce standby current by refreshing only that
part of the memory array required by the host system. The refresh options are full array,
one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of
these partitions can start at either the beginning or the end of the address map (see
Table 6 on page 27). READ and WRITE operations to address ranges receiving refresh will
not be affected. Data stored in addresses not receiving refresh will become corrupted.
When re-enabling additional portions of the array, the new portions are available imme-
diately upon writing to the RCR.
Deep power-down (DPD) operation disables all refresh-related activity. This mode is
used if the system does not require the storage provided by the CellularRAM device. Any
stored data will become corrupted when DPD is enabled. When refresh activity has been
re-enabled by rewriting the RCR, the CellularRAM device will require 150µs to perform
an initialization procedure before normal operations can resume. During this 150µs
period, the current consumption will be higher than the specified standby levels, but
considerably lower than the active current specification.
DPD cannot be enabled or disabled by writing to the RCR using the software access
sequence; the RCR should be accessed using CRE instead.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
Low-Power Operation
©2003 Micron Technology, Inc. All rights reserved.