MT45W4MW16BFB-708 WT TR Micron Technology Inc, MT45W4MW16BFB-708 WT TR Datasheet - Page 60

• Manufacturer Part Number: MT45W4MW16BFB-708 WT TR
• Description: IC PSRAM 64MBIT 70NS 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W4MW16BFB-708 WT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 64M (4M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Revision History
Rev. G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10/05
Rev. F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 04/05
Rev. E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12/04
Rev. D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 09/04
Rev. C, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/04
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
• Added new P25A-specific note on the first page.
• Removed 60ns and 104 MHz support.
• Clarified Note 2, clock state on page 7.
• Clarified data values in Figure 40 on page 51.
• Corrected typographic errors.
• Removed all references to 32Mb density.
• Added Table 9, Maximum Standby Currents for Applying PAR and TCR Settings, on
• Added Table 10, Maximum Standby Currents for Applying PAR and TCR Settings –
• Added Figure 23, Typical Refresh Current vs. Temperature (Itcr), on page 31.
• Added “Maximum and Typical Standby Currents” on page 30.
• WE# LOW limited to
• Last address changed by software access sequence.
• Noted software access third cycle must be CE#-controlled WRITE.
• Separated I
• Moved
• CRE is “Don’t Care” during burst continue.
• Clarified TCR temperatures and setting in Table 9.
• Changed VccQ to 1.7V–3.3V.
• Changed wireless temperature range to -30°C.
• Noted input HIGH voltage not aligned with the workgroup specification of
• Noted wireless temp exceeds the workgroup spec.
• Clarified WAIT assertion for continuous burst with output delay.
• Noted workgroup spec for burst termination compliance.
• Added software access.
• CR WRITE diagram titles updated to reflect WRITEs followed by READ ARRAY opera-
• Added 80 MHz burst clock (-708).
• Changed PAR options to full, one-half, one-quarter, one-eight, or none.
• Corrected Table 17 typo.
• Added Note 3 to Fig. 34 and 40.
• Added
• Clarified READ/WRITE operating currents.
• Added clarifying notes for required refresh opportunity for BCR[15], depending on
• Changed
page 30.
Low-Power (L), on page 30.
tion.
BCR setting.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
t
t
CO to Fig. 46 and Table 44.
CPH to follow CE#-controlled async WRITE cycles only.
t
CEM MAX to 8.
CC
3 for READ and WRITE.
t
CEM for async WRITES.
60
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Revision History
V
CC
Q - 0.4.