MT45W4MW16BFB-708 WT TR Micron Technology Inc, MT45W4MW16BFB-708 WT TR Datasheet - Page 5

• Manufacturer Part Number: MT45W4MW16BFB-708 WT TR
• Description: IC PSRAM 64MBIT 70NS 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W4MW16BFB-708 WT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 64M (4M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

General Description
Figure 2:
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
ADV#
WAIT
WE#
OE#
UB#
CLK
CRE
CE#
LB#
Functional Block Diagram – 4 Meg x 16
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Note:
Control
Logic
Micron
for low-power, portable applications. The MT45W4MW16BFB is a 64Mb DRAM core
device organized as 4 Meg x 16 bits. This device includes an industry-standard burst
mode Flash interface that dramatically increases read/write bandwidth compared with
other low-power SRAM or Pseudo SRAM offerings.
To operate seamlessly on a burst Flash bus, CellularRAM products incorporate a trans-
parent self refresh mechanism. The hidden refresh requires no additional support from
the system memory controller and has no significant impact on device read/write per-
formance.
Two user-accessible control registers define device operation. The bus configuration
register (BCR) defines how the CellularRAM device interacts with the system memory
bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh
configuration register (RCR) is used to control how refresh is performed on the DRAM
array. These registers are automatically loaded with default settings during power-up
and can be updated anytime during normal operation.
Special attention has been focused on standby current consumption during self refresh.
CellularRAM products include three system-accessible mechanisms used to minimize
standby current. Partial-array refresh (PAR) limits refresh to only that part of the DRAM
array that contains essential data. Temperature-compensated refresh (TCR) is used to
adjust the refresh rate according to the case temperature. The refresh rate can be
decreased at lower temperatures to minimize current consumption during standby.
Deep power-down (DPD) halts the refresh operation altogether and is used when no
vital information is stored in the device. These three refresh mechanisms are accessed
through the RCR.
Functional block diagrams illustrate simplified device operation. See truth table, ball
descriptions, and timing diagrams for detailed information.
®
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
CellularRAM™ products are high-speed, CMOS PSRAM memories developed
Refresh Configuration
Bus Configuration
Address Decode
Register (RCR)
Register (BCR)
Logic
5
4,096K x 16
Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Array
DRAM
Output
Buffers
Input/
MUX
and
General Description
©2003 Micron Technology, Inc. All rights reserved.
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