MT45W4MW16BFB-708 WT TR Micron Technology Inc, MT45W4MW16BFB-708 WT TR Datasheet - Page 27

• Manufacturer Part Number: MT45W4MW16BFB-708 WT TR
• Description: IC PSRAM 64MBIT 70NS 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W4MW16BFB-708 WT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 64M (4M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh
Table 6:
Deep Power-Down (RCR[4]) Default = DPD Disabled
Temperature-Compensated Refresh (RCR[6:5]) Default = +85°C Operation
Page Mode Operation (RCR[7]) Default = Disabled
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
RCR[2]
0
0
0
0
1
1
1
1
RCR[1]
64Mb Address Patterns for PAR (RCR[4] = 1)
0
0
1
1
0
0
1
1
RCR[0]
0
1
0
1
0
1
0
1
The PAR bits restrict refresh operation to a portion of the total memory array. This fea-
ture allows the device to reduce standby current by refreshing only that part of the mem-
ory array required by the host system. The refresh options are full array, one-half array,
one-quarter array, one-eighth array, or none of the array. The mapping of these parti-
tions can start at either the beginning or the end of the address map.
The deep power-down bit enables and disables all refresh-related activity. This mode is
used if the system does not require the storage provided by the CellularRAM device. Any
stored data will become corrupted when DPD is enabled. When refresh activity has been
re-enabled, the CellularRAM device will require 150µs to perform an initialization proce-
dure before normal operations can resume.
Deep power-down is enabled when RCR[4] = 0, and remains enabled until RCR[4] is set to
“1.” DPD should not be enabled or disabled with the software access sequence; instead,
use CRE to access the RCR.
The TCR bits allow for adequate refresh at four different temperature thresholds (+15°C,
+45°C, +70°C, and +85°C). The setting selected must be for a temperature higher than
the case temperature of the CellularRAM device. If the case temperature is +50°C, the
system can minimize self refresh current consumption by selecting the +70°C set-
ting. The +15°C and +45°C settings would result in inadequate refreshing and cause
data corruption.
The page mode operation bit determines whether page mode is enabled for asynchro-
nous READ operations. In the power-up default state, page mode is disabled.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
One-quarter of die
One-quarter of die
One-eighth of die
One-eighth of die
Active Section
One-half of die
One-half of die
None of die
Full die
27
000000h–07FFFFh
000000h–3FFFFFh
000000h–1FFFFFh
000000h–0FFFFFh
200000h–3FFFFFh
300000h–3FFFFFh
380000h–3FFFFFh
Address Space
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0
Configuration Registers
4 Meg x 16
2 Meg x 16
1 Meg x 16
0 Meg x 16
2 Meg x 16
1 Meg x 16
512K x 16
521K x 16
Size
©2003 Micron Technology, Inc. All rights reserved.
Density
64Mb
32Mb
16Mb
32Mb
16Mb
8Mb
0Mb
8Mb