MT45W4MW16BFB-708 WT TR Micron Technology Inc, MT45W4MW16BFB-708 WT TR Datasheet - Page 24

• Manufacturer Part Number: MT45W4MW16BFB-708 WT TR
• Description: IC PSRAM 64MBIT 70NS 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W4MW16BFB-708 WT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 64M (4M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 20:
WAIT Polarity (BCR[10]) Default = WAIT Active HIGH
Latency Counter (BCR[13:11]) Default = Three-Clock Latency
Figure 21:
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
DQ[15:0]
DQ[15:0]
DQ[15:0]
A[21:0]
WAIT
WAIT
ADV#
CLK
CLK
V
V
V
V
V
V
V
V
V
V
WAIT Configuration During Burst Operation
Latency Counter
IH
IL
IH
IL
IH
IL
OH
OL
OH
OL
Table 5:
Notes: 1. Clock rates below 50 MHz are allowed as long as
Note:
ADDRESS
VALID
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or
LOW. This bit will determine whether the WAIT signal requires a pull-up or pull-down
resistor to maintain the de-asserted state.
The latency counter bits determine how many clocks occur between the beginning of a
READ or WRITE operation and the first data value transferred. Only latency code two
(three clocks) or latency code three (four clocks) is allowed (see Table 5 and Figure 21)
Latency Configuration
Latency Configuration Code
2 (3 clocks)
3 (4 clocks) – default
Non-default BCR setting for WAIT configuration during burst operation: WAIT active LOW.
Code 3
Code 2
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
D[0]
(Default)
D[1]
24
OUTPUT
VALID
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D[2]
OUTPUT
OUTPUT
VALID
VALID
D[3]
t
CSP specifications are met.
Max Input CLK Frequency (MHz)
OUTPUT
OUTPUT
VALID
53 (18.75ns)
80 (12.50ns)
VALID
DON’T CARE
-708
Configuration Registers
DON’T CARE
D[4]
©2003 Micron Technology, Inc. All rights reserved.
OUTPUT
OUTPUT
VALID
VALID
BCR[8] = 0
Data valid in current cycle.
BCR[8] = 1
Data valid in next cycle.
UNDEFINED
66 (15.20ns)
44
-706/-856
OUTPUT
OUTPUT
1
VALID
VALID
(22.7ns)