IC LCD DVR UNVRSL LOW-MUX 40VSOP

PCF8566T/1,118

Manufacturer Part NumberPCF8566T/1,118
DescriptionIC LCD DVR UNVRSL LOW-MUX 40VSOP
ManufacturerNXP Semiconductors
PCF8566T/1,118 datasheet
 


Specifications of PCF8566T/1,118

Package / Case40-VSOPDisplay TypeLCD
Configuration7 Segment + DP, 14 Segment (24 Segment)InterfaceI²C
Current - Supply30µAVoltage - Supply2.5 V ~ 6 V
Operating Temperature-40°C ~ 85°CMounting TypeSurface Mount
Number Of Digits12Number Of Segments96
Maximum Clock Frequency315 KHzOperating Supply Voltage2.5 V to 6 V
Maximum Power Dissipation400 mWMaximum Operating Temperature+ 85 C
Maximum Supply Current90 uAMinimum Operating Temperature- 40 C
Lead Free Status / RoHS StatusLead free / RoHS CompliantDigits Or Characters-
Other names568-1070-2
935278688118
PCF8566TD-T
  
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PCF8566
Universal LCD driver for low multiplex rates
Rev. 07 — 25 February 2009
1. General description
The PCF8566 is a peripheral device which interfaces to almost any Liquid Crystal Display
(LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed
LCD containing up to four backplanes and up to 24 segments and can easily be cascaded
for larger LCD applications. The PCF8566 is compatible with most microprocessors or
microcontrollers and communicates via a two-line bidirectional I
overheads are minimized by a display RAM with auto-incremented addressing, by
hardware subaddressing and by display memory switching (static and duplex drive
modes).
2. Features
I
Single-chip LCD controller/driver
I
24 segment drives:
N
Up to twelve 7-segment numeric characters including decimal pointer
N
Up to six 14-segment alphanumeric characters
N
Any graphics of up to 96 elements
I
Versatile blinking modes
I
No external components required (even in multiple device applications)
I
Selectable backplane drive configuration: static or 2, 3, 4 backplane multiplexing
I
Selectable display bias configuration: static,
I
Internal LCD bias generation with voltage-follower buffers
I
24
I
Auto-incremented display data loading across device subaddress boundaries
I
Display memory bank switching in static and duplex drive modes
I
LCD and logic supplies may be separated
I
2.5 V to 6 V power supply range
I
Low power consumption
I
Power-saving mode for extremely low power consumption in battery-operated and
telephone applications
I
2
I
C-bus interface
I
TTL and CMOS compatible
I
Compatible with any 4, 8 or 16-bit microprocessor or microcontroller
I
May be cascaded for large LCD applications (up to 1536 segments possible)
I
Cascadable with 40-segment LCD driver PCF8576C
I
Optimized pinning for plane wiring in both and multiple PCF8566 applications
I
Space-saving 40-lead plastic very small outline package (VSO40; SOT158-1)
I
Manufactured in silicon gate CMOS process
4-bit RAM for display data storage
Product data sheet
2
C-bus. Communication
1
1
or
2
3

PCF8566T/1,118 Summary of contents

  • Page 1

    PCF8566 Universal LCD driver for low multiplex rates Rev. 07 — 25 February 2009 1. General description The PCF8566 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive ...

  • Page 2

    ... NXP Semiconductors 3. Ordering information Table 1. Type number PCF8566P PCF8566T PCF8566TS PCF8566U [1] Dark-green version. [2] Chip in tray for chip on board. 4. Marking Table 2. Type number PCF8566P PCF8566T PCF8566TS PCF8566U PCF8566_7 Product data sheet Ordering information Package Name Description DIP40 plastic dual in-line package; 40 leads (600 mil) VSO40 plastic very small outline package ...

  • Page 3

    ... NXP Semiconductors 5. Block diagram LCD BIAS GENERATOR 12 V LCD 4 CLK TIMING BLINKER 3 SYNC 6 OSC OSCILLATOR POWER- RESET SCL INPUT 1 FILTERS SDA Fig 1. Block diagram of PCF8566 PCF8566_7 Product data sheet BP0 BP2 BP1 BP3 BACKPLANE OUTPUTS LCD VOLTAGE SELECTOR PCF8566 DISPLAY CONTROLLER ...

  • Page 4

    ... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Pin configuration for PCF8566 PCF8566_7 Product data sheet Universal LCD driver for low multiplex rates 1 SDA SCL 2 SYNC 3 4 CLK OSC SA0 10 PCF8566 LCD BP0 13 BP2 14 15 BP1 BP3 001aai338 Rev. 07 — 25 February 2009 ...

  • Page 5

    ... NXP Semiconductors Fig 3. Pin configuration for PCF8566U 6.2 Pin description Table 3. Symbol SDA SCL SYNC CLK V DD OSC SA0 LCD PCF8566_7 Product data sheet S10 S11 28 S12 29 30 S13 PCF8566U S14 31 32 S15 S16 33 S17 34 35 S18 Pin description Pin ...

  • Page 6

    ... NXP Semiconductors Table 3. Symbol BP0 BP2 BP1 BP3 S0 to S23 [1] The substrate (rear side of the die) is wired Functional description The PCF8566 is a versatile peripheral device designed to interface any microprocessor or microcontroller to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing backplanes and segments. ...

  • Page 7

    ... NXP Semiconductors Fig 4. Typical system configuration 7.1 Power-on reset At power-on the PCF8566 resets to the following starting conditions: • All backplane outputs are set to V • All segment outputs are set to V • Drive mode 1:4 multiplex with • Blinking is switched off • ...

  • Page 8

    ... NXP Semiconductors Table 5. Preferred LCD drive modes: summary of characteristics LCD drive mode Number of: Backplanes static 1 1:2 multiplex 2 1:2 multiplex 2 1:3 multiplex 3 1:4 multiplex 4 A practical value for V threshold voltage (V the static drive mode a suitable choice is V Multiplex drive modes of 1:3 and 1:4 with hence the contrast ratios are smaller ...

  • Page 9

    ... NXP Semiconductors • 1:4 multiplex with The advantage of these LCD drive modes is a reduction of the LCD full scale voltage V as follows: • 1:3 multiplex ( • 1:4 multiplex ( These compare with It should be noted that V PCF8566_7 Product data sheet Universal LCD driver for low multiplex rates ...

  • Page 10

    ... NXP Semiconductors 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Fig 5. PCF8566_7 Product data sheet V LCD BP0 V SS ...

  • Page 11

    ... NXP Semiconductors 7.4.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCF8566 allows the use of Fig 6. PCF8566_7 Product data sheet 1 1 bias LCD BP0 LCD LCD BP1 LCD LCD LCD Sn LCD LCD ...

  • Page 12

    ... NXP Semiconductors Fig 7. PCF8566_7 Product data sheet V LCD LCD BP0 LCD LCD LCD BP1 LCD LCD LCD LCD LCD LCD S n LCD LCD LCD LCD state LCD LCD V LCD V LCD LCD LCD 0 V state LCD LCD V LCD V ( (t) V (t). state1 Sn BP0 ...

  • Page 13

    ... NXP Semiconductors 7.4.3 1:3 Multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as shown in Fig 8. PCF8566_7 Product data sheet Figure 8. V LCD LCD BP0 LCD LCD LCD BP1 LCD LCD LCD BP2 LCD V SS ...

  • Page 14

    ... NXP Semiconductors 7.4.4 1:4 multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as shown in BP0 BP1 BP2 BP3 Sn Sn+1 Sn+2 Sn+3 state 1 state 2 Fig 9. PCF8566_7 Product data sheet Figure 9. V LCD LCD LCD V SS ...

  • Page 15

    ... NXP Semiconductors 7.5 Oscillator The internal logic and the LCD drive signals of the PCF8566 are timed by the frequency f , which equals either the built-in oscillator frequency f clk f . clk(ext) The clock frequency (f for data reception from the I rate of 100 kHz, f 7.5.1 Internal clock ...

  • Page 16

    ... NXP Semiconductors The lower clock frequency has the disadvantage of increasing the response time when large amounts of display data are transmitted on the I process a display data byte before the next one arrives, it holds the SCL line LOW until the first display data byte is stored. This slows down the transmission rate of the I no data loss occurs ...

  • Page 17

    ... NXP Semiconductors display RAM bits backplane outputs Fig 10. Display RAM bit map showing the direct relationship between display RAM When display data is transmitted to the PCF8566 the display bytes received are stored in the display RAM based on the selected LCD drive mode. An example of a 7-segment numeric display illustrating the storage order for all drive modes is shown in The RAM storage organization applies equally to other LCD types ...

  • Page 18

    LCD segments LCD backplanes a S n+2 BP0 n static n+5 n n+6 BP0 1 ...

  • Page 19

    ... NXP Semiconductors 7.13 Sub-address counter The storage of display data is conditioned by the contents of the subaddress counter. Storage is allowed to take place only when the contents of the subaddress counter match with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is defined by the device select command (see subaddress counter and the hardware subaddress do not match then data storage is blocked but the data pointer will be incremented as if data storage had taken place ...

  • Page 20

    ... NXP Semiconductors Table 7. Blinking mode off additional feature is for an arbitrary selection of LCD segments to be blinked. This applies to the static and 1:2 multiplex drive modes and can be implemented without any communication overheads. Using the output bank selector, the displayed RAM banks are exchanged with alternate RAM banks at the blinking frequency. This mode can also be specifi ...

  • Page 21

    ... NXP Semiconductors 8.1.1.1 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change of the data line, while the clock is HIGH, is defined as the START condition (S). A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP condition (P) ...

  • Page 22

    ... NXP Semiconductors • A master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the master receiver must leave the data line HIGH during the 9th pulse to not acknowledge. The master will now generate a STOP condition. ...

  • Page 23

    ... NXP Semiconductors Fig 16. Slave address structure Two displays controlled by PCF8566 can be recognized on the same I allows: • PCF8566s on the same I Section • The use of two types of LCD multiplex on the same I 2 The I C-bus protocol is shown in condition (S) from the I addresses. All PCF8566s with the same SA0 level acknowledge in parallel to the slave address. All PCF8566s with the alternative SA0 level ignore the whole I After acknowledgement, one or more command bytes (m) follow which defi ...

  • Page 24

    ... NXP Semiconductors 8.3 Command decoder The command decoder identifies command bytes that arrive on the I commands carry a continuation bit C in their most significant bit position as shown in Figure 18. When this bit is set, it indicates that the next byte of the transfer to arrive will also represent a command ...

  • Page 25

    ... NXP Semiconductors Table 10. LCD bias 1 bias 3 1 bias 2 Table 11. Display status disabled (blank) enabled [1] The possibility to disable the display allows implementation of blinking under external control. Table 12. Display status normal mode power saving mode 8.3.2 Load data pointer command Table 13. Description 5 bit binary value ...

  • Page 26

    ... NXP Semiconductors 8.3.5 Blink command Table 16. Blink frequency off Table 17. Blink mode Normal blinking Alternate RAM bank blinking 8.4 Display controller The display controller executes the commands identified by the command decoder. It contains the status registers of the PCF8566 and coordinates their effects. The controller also loads display data into the display RAM as required by the storage order ...

  • Page 27

    ... NXP Semiconductors 10. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (V LCD display artifacts. To avoid such artifacts, V Table 18. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol LCD DD(LCD) P tot stg ...

  • Page 28

    ... NXP Semiconductors 11. Static characteristics Table 19. Static characteristics 2 6 Symbol Parameter Supplies V supply voltage DD V LCD supply voltage LCD I supply current low-power mode supply current DD(lp) Logic V input voltage i V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current OL I leakage current ...

  • Page 29

    ... NXP Semiconductors Table 19. Static characteristics 2 6 Symbol Parameter LCD outputs V voltage on pin voltage on pin output impedance o [1] Outputs open; inputs [2] Resets all logic when V < POR [3] Periodically sampled, not 100 % tested. [4] Outputs measured one at a time. 11.1 Typical supply current characteristics ...

  • Page 30

    ... NXP Semiconductors 11.2 Typical LCD output characteristics + amb Fig 22. Backplane output impedance BP0 to BP3 (R PCF8566_7 Product data sheet Universal LCD driver for low multiplex rates mgg399 ( Fig 23. Segment output impedance S0 to S23 (R BP Rev. 07 — 25 February 2009 PCF8566 mgg400 40 C +25 C +85 C ...

  • Page 31

    ... NXP Semiconductors 12. Dynamic characteristics Table 20. Dynamic characteristics 2 6 Symbol Parameter Clock f clock frequency clk t HIGH-level clock time clk(H) t LOW-level clock time clk(L) t SYNC propagation delay PD(SYNC_N) t SYNC LOW time SYNC_NL t driver propagation delay PD(drv C-bus t bus free time between a STOP and ...

  • Page 32

    ... NXP Semiconductors BP0 to BP3 S0 to S23 Fig 24. Driver timing waveforms SDA SCL SDA Fig 25. I PCF8566_7 Product data sheet t clk(H) CLK SYNC t PD(SYNC_N BUF LOW t HD;STA C-bus timing waveforms Rev. 07 — 25 February 2009 PCF8566 Universal LCD driver for low multiplex rates ...

  • Page 33

    ... NXP Semiconductors 13. Application information 13.1 Cascaded operation Large display configurations sixteen PCF8566s can be recognized on the same 2 I C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable 2 I C-bus slave address (SA0). Table 21. Cluster 1 2 Cascaded PCF8566s are synchronized. They can share the backplane signals from one of the devices in the cascade ...

  • Page 34

    ... NXP Semiconductors V LCD rise bus HOST MICRO- PROCESSOR/ MICRO- CONTROLLER V SS Fig 26. Cascaded PCF8566 configuration The SYNC line is provided to maintain the correct synchronization between all cascaded PCF8566s. This synchronization is guaranteed after the power-on reset. The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments or by defi ...

  • Page 35

    ... NXP Semiconductors Fig 27. Synchronization of the cascade for the various PCF8566 drive modes PCF8566_7 Product data sheet Universal LCD driver for low multiplex rates BP0 SYNC (a) static drive mode. BP0 (1/2 bias) BP0 (1/3 bias) SYNC (b) 1:2 multiplex drive mode. BP0 (1/3 bias) SYNC (c) 1:3 multiplex drive mode ...

  • Page 36

    ... NXP Semiconductors Single plane wiring of packaged PCF8566s is illustrated in SDA 1 SCL 2 SYNC 3 CLK OSC SA0 LCD BP0 13 BP2 14 BP1 15 BP3 BACKPLANES Fig 28. Single plane wiring of packaged PCF8566s PCF8566_7 Product data sheet S23 40 S22 39 S21 38 S20 37 S19 36 S18 35 S17 34 S16 33 S15 32 S14 31 S13 ...

  • Page 37

    ... NXP Semiconductors 14. Package outline DIP40: plastic dual in-line package; 40 leads (600 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.7 0.51 4 inches 0.19 0.02 0.16 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

  • Page 38

    ... NXP Semiconductors VSO40: plastic very small outline package; 40 leads pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.7 0.25 0.1 2.25 0.012 0.096 inches 0.01 0.11 0.004 0.089 Notes 1. Plastic or metal protrusions of 0.4 mm (0.016 inch) maximum per side are not included. ...

  • Page 39

    ... NXP Semiconductors 15. Bare die outline Wire bond die; 40 bonding pads; 2.5 x 2.91 x 0.381 DIMENSIONS (mm are the original dimensions) UNIT max 0.406 mm nom 0.381 2.5 2.91 min 0.356 Notes 1. Pad size 2. Passivation opening OUTLINE VERSION IEC PCF8566U Fig 31. Bare die outline PCF8566U ...

  • Page 40

    ... NXP Semiconductors Table 22. All x/y coordinates represent the position of the center of each pad with respect to the center (x the chip (see Symbol SDA SCL SYNC CLK V DD OSC SA0 LCD BP0 BP2 BP1 BP3 S10 S11 S12 S13 S14 S15 S16 S17 ...

  • Page 41

    ... NXP Semiconductors Table 22. All x/y coordinates represent the position of the center of each pad with respect to the center (x the chip (see Symbol S21 S22 S23 Fig 32. Alignment marks Table 23. Symbol 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling ...

  • Page 42

    ... NXP Semiconductors Fig 33. Tray details Fig 34. Tray alignment Table 24. Symbol PCF8566_7 Product data sheet Tray dimensions Description pocket pitch; x direction pocket pitch; y direction pocket width; x direction pocket width; y direction Rev. 07 — 25 February 2009 PCF8566 Universal LCD driver for low multiplex rates ...

  • Page 43

    ... NXP Semiconductors Table 24. Symbol 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 18.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...

  • Page 44

    ... NXP Semiconductors • Lead-free soldering versus SnPb soldering 18.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • ...

  • Page 45

    ... NXP Semiconductors Fig 35. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 19. Abbreviations Table 27. Acronym CMOS DC HBM LCD MM MSL POR RC RAM RMS SMD TTL PCF8566_7 Product data sheet ...

  • Page 46

    ... Release date PCF8566_7 20090225 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Added U and TS type • Added tray information • ...

  • Page 47

    ... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

  • Page 48

    ... NXP Semiconductors 23. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 6 7.1 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2 LCD bias generator 7.3 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 7 7.4 LCD drive mode waveforms . . . . . . . . . . . . . . 10 7 ...