FAN3224TMPX Fairchild Semiconductor, FAN3224TMPX Datasheet - Page 17

• Manufacturer Part Number: FAN3224TMPX
• Description: IC GATE DVR DUAL 4A 8-MLP
• Manufacturer: Fairchild Semiconductor
• Type: Low Sider

Specifications of FAN3224TMPX

• Configuration: Low-Side
• Input Type: Non-Inverting
• Delay Time: 17ns
• Current - Peak: 5A
• Number Of Configurations: 2
• Number Of Outputs: 2
• Voltage - Supply: 4.5 V ~ 18 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-MLP
• Rise Time: 20 ns
• Fall Time: 17 ns
• Supply Voltage (min): 4.5 V
• Supply Current: 0.95 mA
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Drivers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• High Side Voltage - Max (bootstrap): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: FAN3224TMPXTR

© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.6
Applications Information
Input Thresholds
Each member of the FAN322x driver family consists of
two identical channels that may be used independently
at rated current or connected in parallel to double the
individual current capacity. In the FAN3223 and
FAN3224, channels A and B can be enabled or disabled
independently using ENA or ENB, respectively. The EN
pin has TTL thresholds for parts with either CMOS or
TTL input thresholds. If ENA and ENB are not
connected, an internal pull-up resistor enables the driver
channels by default. ENA and ENB have TTL thresholds
in parts with either TTL or CMOS INx threshold. If the
channel A and channel B inputs and outputs are
connected in parallel to increase the driver current
capacity, ENA and ENB should be connected and
driven together.
The FAN322x family offers versions in either TTL or
CMOS input thresholds. In the FAN322xT, the input
thresholds meet industry-standard TTL-logic thresholds
independent of the V
hysteresis voltage of approximately 0.4V. These levels
permit the inputs to be driven from a range of input logic
signal levels for which a voltage over 2V is considered
logic HIGH. The driving signal for the TTL inputs should
have fast rising and falling edges with a slew rate of
6V/µs or faster, so a rise time from 0 to 3.3V should be
550ns or less. With reduced slew rate, circuit noise
could cause the driver input voltage to exceed the
hysteresis voltage and retrigger the driver input, causing
erratic operation.
In the FAN322xC, the logic input thresholds are
dependent on the V
logic rising edge threshold is approximately 55% of V
and the input falling edge threshold is approximately
38% of V
hysteresis voltage of approximately 17% of V
CMOS inputs can be used with relatively slow edges
(approaching DC) if good decoupling and bypass
techniques are incorporated in the system design to
prevent noise from violating the input voltage hysteresis
window. This allows setting precise timing intervals by
fitting an R-C circuit between the controlling signal and
the IN pin of the driver. The slow rising edge at the IN
pin of the driver introduces a delay between the
controlling signal and the OUT pin of the driver.
Static Supply Current
In the I
(Figure 12 - Figure 14 and Figure 19 - Figure 21), the
curve is produced with all inputs/enables floating (OUT
is low) and indicates the lowest static I
tested configuration. For other states, additional current
flows through the 100k resistors on the inputs and
outputs shown in the block diagram of each part (see
Error! Reference source not found. - Figure 7). In
these cases, the actual static I
obtained from the curves plus this additional current.
DD
DD
(static) typical performance characteristics
. The CMOS input configuration offers a
DD
level and, with V
DD
voltage, and there is a
DD
current is the value
DD
DD
current for the
of 12V, the
DD
. The
DD
17
MillerDrive™ Gate Drive Technology
FAN322x gate drivers incorporate the MillerDrive™
architecture shown in Figure 47. For the output stage, a
combination of bipolar and MOS devices provide large
currents over a wide range of supply voltage and
temperature variations. The bipolar devices carry the
bulk of the current as OUT swings between 1/3 to 2/3
V
LOW rail.
The purpose of the MillerDrive™ architecture is to
speed up switching by providing high current during the
Miller plateau region when the gate-drain capacitance of
the MOSFET is being charged or discharged as part of
the turn-on / turn-off process.
For applications that have zero voltage switching during
the MOSFET turn-on or turn-off interval, the driver
supplies high peak current for fast switching even
though the Miller plateau is not present. This situation
often occurs in synchronous rectifier applications
because the body diode is generally conducting before
the MOSFET is switched ON.
The output pin slew rate is determined by V
and the load on the output. It is not user adjustable, but
a series resistor can be added if a slower rise or fall time
at the MOSFET gate is needed.
Under-Voltage Lockout
The FAN322x start-up logic is optimized to drive
ground-referenced N-channel MOSFETs with an under-
voltage lockout (UVLO) function to ensure that the IC
starts up in an orderly fashion. When V
below the 3.9V operational level, this circuit holds the
output LOW, regardless of the status of the input pins.
After the part is active, the supply voltage must drop
0.2V before the part shuts down. This hysteresis helps
prevent chatter when low V
noise from the power switching. This configuration is not
suitable for driving high-side P-channel MOSFETs
because the low output voltage of the driver would turn
the P-channel MOSFET ON with V
DD
and the MOS devices pull the output to the HIGH or
Figure 47. MillerDrive™ Output Architecture
stage
Input
DD
V
supply voltages have
DD
DD
below 3.9V.
DD
V
OUT
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is rising, yet
DD
voltage