LTC3735EUHF Linear Technology, LTC3735EUHF Datasheet - Page 29

• Manufacturer Part Number: LTC3735EUHF
• Description: IC CTRLR DC/DC 2PH HI EFF 38-QFN
• Manufacturer: Linear Technology

Specifications of LTC3735EUHF

• Applications: Controller, Intel Mobile CPU
• Number Of Outputs: 1
• Voltage - Output: 0.7 ~ 1.71 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 38-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Voltage - Input: -

Figure 14 shows a typical application using the LTC3735
to power the mobile CPU core. The input can vary from 5V
to 24V; the output voltage can be programmed from 0.7V
to 1.708V with a maximum current of 32A. By only
modifying the external MOSFET and inductor selection,
higher load current capability (up to 40A) can be achieved.
The power supply in Figure 14 receives a VRON signal for
ON/OFF control. After soft-start, the output voltage is set
at 1.2V until the assertion of the MCH_PG signal. After
about a 50μs delay, the VID5-VID0 bits gain the control
over the output voltage and program it between 0.7V and
TYPICAL APPLICATIO
5V
V
PGOOD
OA
V
+
RON
Si1034X
470pF
232k
100pF
1μF
X5R
4.7μF
X5R
3.3V
5V
100k
2k
3.3k
SW2
SW1
Figure 14. 5V to 24V Input, 0.7V to 1.708V Output, 32A IMVP-IV Compatible Power Supply
V
CCP
V
OUT
_PG/MCH_PG
0.1μF
0.1μF
1000pF
DPRSLPVR
STP_CPUB
1M
BAT54
47pF
PSIB
VID0
VID1
VID2
VID3
VID4
VID5
470pF
36
19
20
21
22
23
24
35
17
16
28
34
31
U
2
8
4
3
9
1
MCH_PG
DPRSLPVR
STP_CPUB
PSIB
FREQSET
VID0
VID1
VID2
VID3
VID4
VID5
PGOOD
I
RUN/SS
SGND
V
PV
BOOST1
BOOST2
TH
FB
CC
LTC3735
RDPRSLP
SENSE1
SENSE1
SENSE2
SENSE2
RDPSLP
RBOOT
OAOUT
PGND
V
V
SW1
SW2
TG1
BG1
TG2
BG2
OA
OA
+
–
+
–
+
–
33
32
27
26
10
11
30
29
25
12
13
18
14
15
5
7
6
56.2k
13.3k
1nF
1nF
1.27M
12.7k
Q1
Q2
Q3
Q4
1.708V. When the STP_CPUB signal is low, a deep sleep
state is indicated and the output voltage is decreased by
about 1.04%. When the DPRSLPVR signal is high, a
deeper sleep state is indicated and the output voltage
becomes 0.748V regardless of the states of the VID bits.
Active voltage positioning is accomplished with a resistor
from the I
steeper AVP slope while higher resistance provides a
flatter slope. Finally, the PGOOD output is masked for
110μs during VID change or state transition.
10Ω
1M 1%
549k
1μF
1μF
D1
D2
V
OA
0.8μH
0.8μH
13.3k
10Ω
+
100Ω
L1
L2
PSIB
S1
TH
S1
S2
0.002Ω
0.002Ω
10Ω
+
100Ω
+
+
to the V
S2
+
10Ω
C5: PANSONIC SP CAPS EEFSX0D181R
D1, D2: B340A
L1, L2: CDEP 104-OR8MC-L
Q1, Q3: IRF7811W OR Si7860DP
Q2, Q4: IRF7811W ×2 OR Si7856DP
3.3V
OR SANYO POSCAP 2R5TPE220M9
OA
249k
80.6k
1M
+
MMBT3904
pin. Lower resistance yields a
PGOOD
2.2μF
2N7002
OPTIONAL INTERFACE
+
3.3V
2k
C1
10μF ×4
35V X5R
C5
×3
CLK_EN#
BAT54C
4.12k
43.2k
V
LTC3735
1μF
RON
3.3V
V
5V ~ 24V
V
0.7V ~ 1.708V
AT 32A
MMBT3904
IN
OUT
1.9k
29
IMVP4_PG
3735f
3735 F14