LM25088MH-1/NOPB National Semiconductor, LM25088MH-1/NOPB Datasheet - Page 10

• Manufacturer Part Number: LM25088MH-1/NOPB
• Description: IC CTLR BUCK NON-SYNC 16-TSSOP
• Manufacturer: National Semiconductor
• Series: PowerWise®r
• Type: Step-Down (Buck)r

Specifications of LM25088MH-1/NOPB

• Design Resources: LM(2)5088-1/2 QS Component Calculator
• Internal Switch(s): No
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 1.21 ~ 45 V
• Current - Output: 10A
• Frequency - Switching: 200kHz, 500kHz
• Voltage - Input: 4.5 ~ 42 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP Exposed Pad, 16-eTSSOP, 16-HTSSOP
• Primary Input Voltage: 42V
• No. Of Outputs: 1
• Output Voltage: 1.2V
• Output Current: 10A
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +125°C
• Msl: MSL 1 - Unlimited
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Other names: LM25088MH-1

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Detailed Operation
The LM25088 Wide Input Range Buck Controller features all
the functions necessary to implement an efficient high voltage
step-down converter using a minimum number of external
components. The control method is based on peak current
mode control utilizing an emulated current ramp. Peak current
mode control provides inherent line voltage feed-forward, cy-
cle-by-cycle current limiting and ease of loop compensation.
The use of an emulated control ramp reduces noise sensitivity
of the pulse-width modulation circuit, allowing reliable pro-
cessing of very small duty cycles necessary in high input
voltage applications. The operating frequency is user pro-
grammable from 50 kHz to 1 MHz. The LM25088-1 provides
a ±5% frequency dithering function to reduce the conducted
and radiated EMI, while the LM25088-2 provides a versatile
restart timer for overload protection. Additional features in-
clude the low dropout bias regulator, tri-level enable input to
control shutdown and standby modes, soft-start, and voltage
tracking and oscillator synchronization capability. The device
is available in a thermally enhanced TSSOP-16EP pin pack-
age.
The functional block diagram and typical application schemat-
ic of the LM25088 are shown in figure 1. The LM25088 is well
suited for a wide range of applications where efficient step-
down of high, unregulated input voltage is required. The
LM25088’s typical applications include Telecom, Industrial
and Automotive.
High Voltage Low-Dropout
Regulator
The LM25088 contains a high voltage, low-dropout regulator
that provides the VCC bias supply for the controller and the
bootstrap MOSFET gate driver. The input pin (VIN) can be
connected directly to an input voltage as high as 42V. The
output of the VCC regulator (7.8V) is internally current limited
to 25 mA. Upon power up, the regulator sources current into
the capacitor connected to the VCC pin. When the voltage at
the VCC pin exceeds the upper VCC UV threshold of 4.0V
and the EN pin is greater than 1.2 Volts, the output (HG) is
enabled and a soft-start sequence begins. The output is ter-
minated if VCC falls below its lower UV threshold (3.8V) or
the EN pin falls below 1.1V. When VIN is less than VCC reg-
ulation point of 7.8V, then the internal pass device acts as a
switch. Thereby, VCC tracks VIN with a voltage drop deter-
mined by the R
current of the controller. The required VCC capacitor value is
dependant on system startup characteristics with a minimum
value no less than 0.1 µF.
An auxiliary supply voltage can be applied to the VCC pin to
reduce the IC power dissipation. If the auxiliary voltage is
greater than 8.2V, the internal regulator will be disabled. The
VCC regulator series pass transistor includes a diode be-
tween VCC and VIN that should not be forward biased in
normal operation.
In high voltage applications, additional care should be taken
to ensure that the VIN pin does not exceed the absolute max-
DS(ON)
of the internal switch and operating
10
imum voltage rating of 45V. During line or load transients,
voltage ringing on the VIN pin that exceeds the absolute max-
imum ratings may damage the IC. Both careful PC board
layout and the use of high quality bypass capacitors located
close to the VIN and GND pins are essential.
Line Under-Voltage Detector
The LM25088 contains a dual level under-voltage lockout
(UVLO) circuit. When the EN pin is below 0.4V, the controller
is in a low current shutdown mode. When the EN pin is greater
than 0.4V but less than 1.2V, the controller is in a standby
mode. In standby mode the VCC regulator is active but the
output switch is disabled and the SS pin is held low. When the
EN pin exceeds 1.2V and VCC exceeds the VCC UV thresh-
old, the SS pin and the output switch is enabled and normal
operation begins. An internal 5 µA pull-up current source at
the EN pin configures the controller to be fully operational if
the EN pin is left open.
An external VIN UVLO set-point voltage divider from VIN to
GND can be used to set the minimum startup input voltage of
the controller. The divider must be designed such that the
voltage at the EN pin exceeds 1.2V (typ) when VIN is in the
desired operating range. The internal 5 µA pull-up current
source must be included in calculations of the external set-
point divider. 100 mV of hysteresis is included for both the
shutdown and standby thresholds. The EN pin is internally
connected to a 1 kΩ resistor and an 8V zener clamp. If the
voltage at the EN pin exceeds 8V, the bias current for the EN
pin will increase at the rate of 1mA/V. The voltage at the EN
pin should never exceed 14V.
Oscillator and Sync Capability
The LM25088 oscillator frequency is set by a single external
resistor connected between the RT pin and the GND pin. The
R
a desired oscillator frequency (f
R
The RT pin can also be used to synchronize the internal os-
cillator to an external clock. The internal oscillator is synchro-
nized to an external clock by AC coupling a positive edge into
the RT/SYNC pin. The RT/SYNC pin voltage must exceed 3V
to trip the internal clock synchronization pulse detector. The
free-running frequency should be set nominally 15% below
the external clock frequency and the pulse width applied to
the RT/SYNC pin must be less than 150ns. Synchronization
to an external clock more than twice the free-running fre-
quency can produce abnormal behavior of the pulse-width
modulator.
T
T
resistor should be located very close to the device. To set
resistor can be calculated from the following equation:
SW
), the necessary value of