DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 12

• Manufacturer Part Number: DK-DEV-1AGX60N
• Description: KIT DEV ARRIA GX 1AGX60N
• Manufacturer: Altera
• Series: Arria GXr
• Type: FPGAr

Specifications of DK-DEV-1AGX60N

• Contents: Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
• For Use With/related Products: 1AGX60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2372

2–6
Figure 2–5. Byte Serializer Operation
Note to
(1) datain may be 16 or 20 bits. dataout may be 8 or 10 bits.
Arria GX Device Handbook, Volume 1
Figure
datain[15:0]
dataout[7:0]
2–5:
f
Figure 2–5
byte serializer from the transmitter phase compensation FIFO; dataout[7:0] is the
output of the byte serializer.
8B/10B Encoder
The 8B/10B encoder block is used in all supported functional modes. The 8B/10B
encoder block takes in 8-bit data from the byte serializer or the transmitter phase
compensation FIFO buffer. It generates a 10-bit code group with proper running
disparity from the 8-bit character and a 1-bit control identifier (tx_ctrlenable).
When tx_ctrlenable is low, the 8-bit character is encoded as data code group
(Dx.y). When tx_ctrlenable is high, the 8-bit character is encoded as a control
code group (Kx.y). The 10-bit code group is fed to the serializer. The 8B/10B encoder
conforms to the IEEE 802.3 1998 edition standard.
For additional information regarding 8B/10B encoding rules, refer to the
and Additional Information
Figure 2–6
Figure 2–6. 8B/10B Encoder
During reset (tx_digitalreset), the running disparity and data registers are
cleared and the 8B/10B encoder continously outputs a K28.5 pattern from the
RD-column. After out of reset, the 8B/10B encoder starts with a negative disparity
(RD-) and transmits three K28.5 code groups for synchronizing before it starts
encoding the input data or control character.
xxxxxxxxxx
shows byte serializer input and output. datain[15:0] is the input to the
shows the 8B/10B conversion format.
{8'h00,8'h01}
(Note 1)
D1
MSB
xxxxxxxxxx
9
j
chapter.
h
8
H
7
g
7
G
6
8'h01
D1
{8'h02,8'h03}
8B-10B Conversion
6
LSByte
5
F
f
D2
E
4
5
i
8'h00
3
D
e
D1
4
MSByte
2
C
d
3
B
1
c
8'h03
2
D2
0
A
b
LSByte
1
© December 2009 Altera Corporation
xxxx
LSB
D3
a
0
Chapter 2: Arria GX Architecture
Ctrl
8'h02
D2
MSByte
Specifications
Transceivers