DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 218

• Manufacturer Part Number: DK-DEV-1AGX60N
• Description: KIT DEV ARRIA GX 1AGX60N
• Manufacturer: Altera
• Series: Arria GXr
• Type: FPGAr

Specifications of DK-DEV-1AGX60N

• Contents: Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
• For Use With/related Products: 1AGX60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2372

4–96
DCD Measurement Techniques
Figure 4–11. DCD Measurement Technique for Non-DDIO (Single-Data Rate) Outputs
Arria GX Device Handbook, Volume 1
Figure 4–10. Duty Cycle Distortion
DCD expressed in absolution derivation, for example, D1 or D2 in
clock-period independent. DCD can also be expressed as a percentage, and the
percentage number is clock-period dependent. DCD as a percentage is defined as:
DCD is measured at an FPGA output pin driven by registers inside the corresponding
I/O element (IOE) block. When the output is a single data rate signal (non-DDIO),
only one edge of the register input clock (positive or negative) triggers output
transitions
caused by the clock input buffer or different input I/O standard does not transfer to
the output signal.
However, when the output is a double data rate input/output (DDIO) signal, both
edges of the input clock signal (positive and negative) trigger output transitions
(Figure
affect the output DCD.
(T/2 – D1) / T (the low percentage boundary)
(T/2 + D2) / T (the high percentage boundary)
4–12). Therefore, any distortion on the input clock and the input clock buffer
(Figure
4–11). Therefore, any DCD present on the input clock signal or
CLKH = T/2
Falling Edge A
Ideal Falling Edge
Clock Period (T)
D1
D2
Falling Edge B
CLKL = T/2
Chapter 4: DC and Switching Characteristics
© December 2009 Altera Corporation
Figure
Duty Cycle Distortion
4–10, is