DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 16

• Manufacturer Part Number: DK-DEV-1AGX60N
• Description: KIT DEV ARRIA GX 1AGX60N
• Manufacturer: Altera
• Series: Arria GXr
• Type: FPGAr

Specifications of DK-DEV-1AGX60N

• Contents: Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
• For Use With/related Products: 1AGX60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2372

2–10
Receiver Path
Arria GX Device Handbook, Volume 1
Programmable Pre-Emphasis
The programmable pre-emphasis module controls the output driver to boost high
frequency components and compensate for losses in the transmission medium, as
shown in
Figure 2–10. Pre-Emphasis Signaling
Pre-emphasis percentage is defined as (V
differential emphasized voltage (peak-to-peak) and V
steady-state voltage (peak-to-peak).
PCI Express (PIPE) Receiver Detect
The Arria GX transmitter buffer has a built-in receiver detection circuit for use in PCI
Express (PIPE) mode. This circuit provides the ability to detect if there is a receiver
downstream by sending out a pulse on the channel and monitoring the reflection.
This mode requires a tri-stated transmitter buffer (in electrical idle mode).
PCI Express (PIPE) Electric Idles (or Individual Transmitter Tri-State)
The Arria GX transmitter buffer supports PCI Express (PIPE) electrical idles. This
feature is only active in PCI Express (PIPE) mode. The tx_forceelecidle port puts
the transmitter buffer in electrical idle mode. This port is available in all PCI Express
(PIPE) power-down modes and has specific usage in each mode.
This section describes the data path through the Arria GX receiver. The sub-blocks are
described in order from the receiver buffer to the PLD-receiver parallel interface.
Receiver Buffer
The Arria GX receiver input buffer supports the 1.2-V and 1.5-V PCML I/O standards
at rates up to 3.125 Gbps. The common mode voltage of the receiver input buffer is
programmable between 0.85 V and 1.2 V. You must select the 0.85 V common mode
voltage for AC- and DC-coupled PCML links and 1.2 V common mode voltage for
DC-coupled LVDS links.
Figure
2–10. Pre-emphasis is set statically using the ALTGXB megafunction.
Pre-Emphasis % = (
V
MAX
V
V
MAX
V
MAX
MIN
MIN
/V
− 1) × 100
MIN
– 1) × 100, where V
MIN
is the differential
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
M AX
is the
Transceivers