DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 21

• Manufacturer Part Number: DK-DEV-1AGX60N
• Description: KIT DEV ARRIA GX 1AGX60N
• Manufacturer: Altera
• Series: Arria GXr
• Type: FPGAr

Specifications of DK-DEV-1AGX60N

• Contents: Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
• For Use With/related Products: 1AGX60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2372

Chapter 2: Arria GX Architecture
Transceivers
Figure 2–15. Word Aligner
© December 2009 Altera Corporation
f
Once a pattern is detected and the data bus is aligned, the word boundary is locked.
The two detection status signals (rx_syncstatus and rx_patterndetect)
indicate that an alignment is complete.
Figure 2–15
Control and Status Signals
The rx_enapatternalign signal is the FPGA control signal that enables word
alignment in non-automatic modes. The rx_enapatternalign signal is not used in
automatic modes (PCI Express [PIPE], XAUI, GIGE, and Serial RapidIO).
In manual alignment mode, after the rx_enapatternalign signal is activated, the
rx_syncstatus signal goes high for one parallel clock cycle to indicate that the
alignment pattern has been detected and the word boundary has been locked. If
rx_enapatternalign is deactivated, the rx_syncstatus signal acts as a
re-synchronization signal to signify that the alignment pattern has been detected but
not locked on a different word boundary.
When using the synchronization state machine, the rx_syncstatus signal indicates
the link status. If the rx_syncstatus signal is high, link synchronization is
achieved. If the rx_syncstatus signal is low, link synchronization has not yet been
achieved, or there were enough code group errors to lose synchronization.
For more information about manual alignment modes, refer to the
Handbook.
The rx_patterndetect signal pulses high during a new alignment and whenever
the alignment pattern occurs on the current word boundary.
Programmable Run Length Violation
The word aligner supports a programmable run length violation counter. Whenever
the number of the continuous ‘0’ (or ‘1’) exceeds a user programmable value, the
rx_rlv signal goes high for a minimum pulse width of two recovered clock cycles.
The maximum run values supported are 128 UI for 8-bit serialization or 160 UI for
10-bit serialization.
Running Disparity Check
The running disparity error rx_disperr and running disparity value
rx_runningdisp are sent along with aligned data from the 8B/10B decoder to the
FPGA. You can ignore or act on the reported running disparity value and running
disparity error signals.
is a block diagram of the word aligner.
datain
bitslip
enapatternalign
clock
Aligner
Word
patterndetect
syncstatus
dataout
Arria GX Device Handbook, Volume 1
Arria GX Device
2–15