DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 133
DK-DEV-1AGX60N
Manufacturer Part Number
DK-DEV-1AGX60N
Description
KIT DEV ARRIA GX 1AGX60N
Manufacturer
Altera
Series
Arria GXr
Type
FPGAr
Datasheet
1.EP1AGX20CF484C6N.pdf
(234 pages)
Specifications of DK-DEV-1AGX60N
Contents
Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
For Use With/related Products
1AGX60N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2372
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 133 of 234
- Download datasheet (4Mb)
Chapter 4: DC and Switching Characteristics
Operating Conditions
Table 4–7. Arria GX Transceiver Block AC Specification
© December 2009 Altera Corporation
SDI Receiver Jitter Tolerance
Sinusoidal Jitter Tolerance
(peak-to-peak)
Sinusoidal Jitter Tolerance
(peak-to-peak)
Notes to
(1) Dedicated REFCLK pins were used to drive the input reference clocks.
(2) Jitter numbers specified are valid for the stated conditions only.
(3) Refer to the protocol characterization documents for detailed information.
(4) The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.
(5) The jitter numbers for PCI Express are compliant to the PCIe Base Specification 2.0.
(6) The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3.
(7) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
(8) The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M specifications.
Table
4–7:
Description
(8)
Jitter Frequency = 15 KHz
Data Rate = 2.97 Gbps (3G)
REFCLK
Pattern = Single Line
Scramble Color Bar
No Equalization
DC Gain = 0 dB
Jitter Frequency = 100 KHz
Data Rate = 2.97 Gbps (3G)
REFCLK
Pattern = Single Line Scramble Color Bar
No Equalization
DC Gain = 0 dB
Jitter Frequency = 148.5 MHz
Data Rate = 2.97 Gbps (3G)
REFCLK
Pattern = Single Line
Scramble Color Bar
No Equalization
DC Gain = 0 dB
Jitter Frequency = 20 KHz
Data Rate = 1.485 Gbps (HD)
REFCLK
Pattern = 75% Color Bar
No Equalization
DC Gain = 0 dB
Jitter Frequency = 100 KHz
Data Rate = 1.485 Gbps (HD)
REFCLK
Pattern = 75% Color Bar
No Equalization
DC Gain = 0 dB
= 148.5 MHz
= 148.5 MHz
= 74.25 MHz
= 74.25 MHz
= 148.5 MHz
(Note
1), (2),
Condition
(3)
(Part 4 of 4)
Arria GX Device Handbook, Volume 1
–6 Speed Grade
Commercial &
Industrial
> 0.3
> 0.3
> 0.2
> 2
> 1
Units
UI
UI
UI
UI
UI
4–11
Related parts for DK-DEV-1AGX60N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV STRATIX IV FPGA 4SE530
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV FPGA 2AGX260 W/6.375G TX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV MAX V 5M570Z
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX III
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT STARTER CYCLONE IV GX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: