DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 74

• Manufacturer Part Number: DK-DEV-1AGX60N
• Description: KIT DEV ARRIA GX 1AGX60N
• Manufacturer: Altera
• Series: Arria GXr
• Type: FPGAr

Specifications of DK-DEV-1AGX60N

• Contents: Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
• For Use With/related Products: 1AGX60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2372

2–68
Figure 2–55. Regional Clocks
Arria GX Device Handbook, Volume 1
Dual-Regional Clock Network
A single source (CLK pin or PLL output) can generate a dual-RCLK by driving two
RCLK network lines in adjacent quadrants (one from each quadrant), which allows
logic that spans multiple quadrants to use the same low skew clock. The routing of
this clock signal on an entire side has approximately the same speed but slightly
higher clock skew when compared with a clock signal that drives a single quadrant.
Internal logic-array routing can also drive a dual-regional clock. Clock pins and
enhanced PLL outputs on the top and bottom can drive horizontal dual-regional
clocks. Clock pins and fast PLL outputs on the left and right can drive vertical
dual-regional clocks, as shown in
dual-regional clocks.
CLK[3..0]
7
1
2
8
RCLK
RCLK
[3..0]
[7..4]
[31..28]
RCLK
RCLK
[11..8]
CLK[15..12]
CLK[7..4]
11 5
12 6
Figure
[27..24]
[15..12]
RCLK
RCLK
2–56. Corner PLLs cannot drive
[23..20]
[19..16]
RCLK
RCLK
Transceiver
Transceiver
Arria GX
Arria GX
Block
Block
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
PLLs and Clock Networks