DK-DEV-1AGX60N Altera, DK-DEV-1AGX60N Datasheet - Page 58

• Manufacturer Part Number: DK-DEV-1AGX60N
• Description: KIT DEV ARRIA GX 1AGX60N
• Manufacturer: Altera
• Series: Arria GXr
• Type: FPGAr

Specifications of DK-DEV-1AGX60N

• Contents: Dev. Board, Quartus® II Web Edition, Reference Designs, Labs, and Complete Documentation
• For Use With/related Products: 1AGX60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2372

2–52
Figure 2–44. M4K RAM Block Control Signals
Arria GX Device Handbook, Volume 1
Dedicated
Row LAB
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
The R4, C4, and direct link interconnects from adjacent LABs drive the M4K RAM
block local interconnect. The M4K RAM blocks can communicate with LABs on either
the left or right side through these row resources or with LAB columns on either the
right or left with the column resources. Up to 16 direct link input connections to the
M4K RAM block are possible from the left adjacent LABs and another 16 are possible
from the right adjacent LAB. M4K RAM block outputs can also connect to left and
right LABs through direct link interconnect.
to logic array interface.
6
clock_a
clock_b
clocken_a
clocken_b
Figure 2–45
renwe_a
renwe_b
shows the M4K RAM block
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
aclr_a
aclr_b
TriMatrix Memory