dp83902a National Semiconductor Corporation, dp83902a Datasheet
dp83902a
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dp83902a Summary of contents
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... The transceiver when combined with equalization resistors transmit receive filters and pulse transformers provides a complete physical interface from the DP83902A’s ENDEC module and the twisted pair medium The integrated ENDEC module allows Manchester encod- ...
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... DMA channels and an internal FIFO Bus arbitration and memory control logic are integrated to reduce board cost and area overheads DP83902A provides a comprehensive single chip solution for 10BASE-T IEEE 802 3 networks and is designed for easy interface to other transceivers via the AUI interface ...
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... Connection Diagrams (Continued) Order Number DP83902AVLJ See NS Package Number VLJ100A 11157 – 56 ...
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... This allows asynchronous transfer of data from the system memory to local memory I REGISTER ADDRESS These four pins are used to select a register to be read or written The state of these inputs is ignored when the DP83902A is not in slave mode (CS high 11157 – 65 ...
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... Active during read cycles (t2 t3 tw) to buffer memory Input data must be valid on rising edge of MRD TRI-STATE until BACK asserted I SLAVE WRITE STROBE Strobe from CPU to write an internal register selected by RA0 – RA3 Data is latched into the DP83902A on the rising edge of this input I SLAVE READ STROBE Strobe from CPU to read an internal register selected by RA0 – ...
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... I O GOOD LINK LINK DISABLE This pin has a dual function both input and output The function is latched by the DP83902A on the rising edge of the Reset signal the chip returning to normal operation after reset As an output this pin is configured as an open drain N-channel device and is ...
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... CD transceiver SNISEL I FACTORY TEST INPUT For normal operation tied to V enables the ENDEC module to be tested independently of the DP83902A module CRS O CARRIER SENSE RECEIVE A TTL MOS level active high signal asserted for approximately 50 ms whenever valid transmit or receive data is detected while in AUI mode or receive data is detected while in ...
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Block Diagram Typical Connection to Twisted Pair Cable Recommended integrated modules are 1) Pulse Engineering PE65431 2) Belfuse 0556-2006-01 or 0556-3392-00 3) Valor FL1012 FIGURE 1 ST-NIC Twisted Pair Interface 11157 – ...
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Functional Description TWISTED PAIR INTERFACE (TPI) MODULE The TPI consists of five main logical functions a) The Smart Squelch responsible for determining when valid data is present on the differential receive inputs (RXI The Collision ...
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... Signals more negative than coded Data becomes valid typically within 5 bit times The DP83902A may tolerate bit jitter the received data The decoder detects the end of a frame when no more mid-bit transitions are detected COLLISION TRANSLATOR ...
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Functional Description In order to prevent distortion on the transmitted frequency the total capacitance seen by the crystal should equal the total load capacitance On a standard parallel set-up as shown in the diagram below the 2 load ...
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Functional Description 3 ST-NIC flushes remaining bytes from FIFO 4 ST-NIC performs internal processing to prepare for writ- ing the header 5 ST-NIC writes 4-byte (2-word) header 6 ST-NIC de-asserts BREQ FIFO Threshold Detection To assure that no ...
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... Direct Memory Access Control (DMA) The DMA capabilities of the ST-NIC greatly simplify the use of the DP83902A in typical configurations The local DMA channel transfers data between the FIFO and memory On transmission the packet is DMAed from memory to the FIFO in bursts Should a collision occur ( times) the ...
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Packet Reception The Local DMA receive channel uses a Buffer Ring Struc- ture comprised of a series of contiguous fixed length 256-byte (128 word) buffers for storage of received packets The location of the Receive Buffer Ring is ...
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Packet Reception (Continued) INITIALIZATION OF THE BUFFER RING Two static registers and two working registers control the operation of the Buffer Ring These are the Page Start Reg- ister Page Stop Register (both described previously) the Current Page ...
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Packet Reception (Continued) LINKING RECEIVE BUFFER PAGES If the length of the packet exhausts the first 256-byte buffer the DMA performs a forward link to the next buffer to store the remainder of the packet For a maximum ...
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Packet Reception (Continued) Buffer Ring Overflow If the Buffer Ring has been filled and the DMA reaches the Boundary Pointer Address reception of the incoming pack- et will be aborted by the ST-NIC Thus the packets previ- ously ...
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Packet Reception (Continued) 6 Place the ST-NIC in either mode 1 or mode 2 loopback This can be accomplished by setting bits D2 and D1 of the Transmit Configuration Register to ‘‘0 1’’ or ‘‘1 0’’ respectively 7 ...
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Packet Reception (Continued) Enabling the ST-NIC On An Active Network After the ST-NIC has been initialized the procedure for dis- abling and then re-enabling the ST-NIC on the network is similar to handling Receive Buffer Ring overflow as ...
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Packet Reception (Continued) BUFFER RECOVERY FOR REJECTED PACKETS If the packet is a runt packet or contains CRC or Frame Alignment errors it is rejected The buffer management log- ic resets the DMA back to the first buffer ...
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Packet Reception (Continued) REMOVING PACKETS FROM THE RING Packets are removed from the ring using the Remote DMA or an external device When using the Remote DMA the Send Packet command can be used This programs the Re- ...
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Packet Transmission The Local DMA is also used during transmission of a pack- et Three registers control the DMA transfer during trans- mission a Transmit Page Start Address Register (TPSR) and the Transmit Byte Count Registers (TBCR0 1) ...
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Remote DMA The Remote DMA channel is used to both assemble pack- ets for transmission and to remove received packets from the Receive Buffer Ring It may also be used as a general purpose slave DMA channel for ...
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Internal Registers All registers are 8-bit wide and mapped into four pages which are selected in the Command Register (PS0 PS1) Pins RA0 – RA3 are used to address registers within each page Page 0 registers are those ...
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Internal Registers (Continued) e Page 1 Address Assignments (PS1 0 PS0 RA0 – RA3 RD 00H Command (CR) Command (CR) 01H Physical Address Physical Address Register 0 (PAR0) Register 0 (PAR0) 02H Physical Address Physical Address Register 1 ...
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Internal Registers (Continued REGISTER DESCRIPTIONS COMMAND REGISTER (CR) 00H (READ WRITE) The Command Register is used to initiate transmissions enable or disable Remote DMA operations and to select register pages To issue a command the microprocessor ...
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Internal Registers (Continued REGISTER DESCRIPTIONS (Continued) INTERRUPT STATUS REGISTER (ISR) This register is accessed by the host processor to determine the cause of an interrupt Any interrupt can be masked in the Interrupt Mask Register (IMR) ...
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Internal Registers (Continued REGISTER DESCRIPTIONS (Continued) INTERRUPT MASK REGISTER (IMR) 0FH (WRITE) The Interrupt Mask Register is used to mask interrupts Each interrupt mask bit corresponds to a bit in the Interrupt Status Register (ISR) If ...
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Internal Registers (Continued REGISTER DESCRIPTIONS (Continued) DATA CONFIGURATION REGISTER (DCR) This Register is used to program the ST-NIC for 8- or 16-bit memory interface select byte ordering in 16-bit applications and establish FIFO thresholds The DCR ...
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Internal Registers (Continued REGISTER DESCRIPTIONS (Continued) TRANSMIT CONFIGURATION REGISTER (TCR) The transmit configuration establishes the actions of the transmitter section of the ST-NIC during transmission of a packet on the network LB1 and LB0 which select ...
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Internal Registers (Continued REGISTER DESCRIPTIONS (Continued) TRANSMIT STATUS REGISTER (TSR) 04H (READ) This register records events that occur on the media during transmission of a packet It is cleared when the next transmission is initiated by ...
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Internal Registers (Continued REGISTER DESCRIPTIONS (Continued) RECEIVE CONFIGURATION REGISTER (RCR) This register determines operation of the ST-NIC during reception of a packet and is used to program what types of packets to accept 7 Bit Symbol ...
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Internal Registers (Continued REGISTER DESCRIPTIONS (Continued) RECEIVE STATUS REGISTER (RSR) 0CH (READ) This register records status of the received packet including information on errors and the type of address match either physical or multicast The contents ...
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Internal Registers (Continued DMA REGISTERS The DMA Registers are partitioned into groups Transmit Receive and Remote DMA Registers The Transmit regis- ters are used to initialize the Local DMA Channel for trans- mission of packets while ...
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Internal Registers (Continued LOCAL DMA RECEIVE REGISTERS PAGE START AND STOP REGISTERS (PSTART PSTOP) The Page Start and Page Stop Registers program the start- ing and stopping address of the Receive Buffer Ring Since the ST-NIC ...
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Internal Registers (Continued) cant bits of the CRC generator are latched These 6 bits are then decoded decode to index a unique filter bit (FB0 – 63) in the multicast address registers If ...
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Initialization Procedures The ST-NIC must be initialized prior to transmission or re- ception of packets from the network Power on reset is ap- plied to the ST-NIC’s reset pin This clears sets the follow- ing bits Register Reset ...
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... Upper Byte Count LOOPBACK TESTS Loopback capabilities are provided to allow certain tests to be performed to validate operation of the DP83902A ST- NIC prior to transmitting and receiving packets on a live network Typically these tests may be performed during power node The diagnostic provides support to veri- ...
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Loopback Diagnostics 3 Verify that the Address Recognition Logic can a) Recognize address match packets b) Reject packets that fail to match an address LOOPBACK OPERATION IN THE ST-NIC Loopback is a modified form of transmission using only ...
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Loopback Diagnostics Since errored packets can be rejected the status associat- ed with these packets is lost unless the CPU can access the Receive Status Register before the next packer arrives In situations where another packet arrives very ...
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Bus Arbitration and Timing The ST-NIC operates in three possible modes BUS MASTER (WHILE PERFORMING DMA) BUS SLAVE (WHILE BEING ACCESSED BY CPU) IDLE Upon power-up the ST-NIC indeterminate state Af- ter ...
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Bus Arbitration and Timing Note In 32-bit address mode ADS1 is at TRI-STATE after the first T1–T4 states thus pull-down resistor is required for 32-bit address (Continued) 16-Bit Address 16-Bit Data 32-Bit Address 8-Bit Data ...
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Bus Arbitration and Timing When in 32-bit mode four additional BSCK cycles are re- quired per burst The first bus cycle (T1 – each burst is used to output the upper 16-bit addresses This 16-bit ...
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Bus Arbitration and Timing mine whether the packet matches its Physical Address Reg- isters or maps to one of its Multicast Registers This causes the FIFO to accumulate 8 bytes Furthermore there are some synchronization delays in the ...
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Bus Arbitration and Timing The FIFO at the Beginning of Transmit Before transmitting the ST-NIC performs a prefetch from memory to load the FIFO The number of bytes prefetched Maximum Bus Latency for Byte Mode (Continued) is the ...
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Bus Arbitration and Timing REMOTE DMA-BIDIRECTIONAL PORT CONTROL The Remote DMA transfers data between the local buffer memory and a bidirectional port (memory transfer) This transfer is arbited on a byte by byte basis versus ...
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Bus Arbitration and Timing REMOTE WRITE TIMING A Remote Write operation transfers data from the I O port to the local buffer RAM The ST-NIC initiates a transfer by requesting a byte word via the PRQ The system ...
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Bus Arbitration and Timing An additional caution for high speed systems is that the polling must follow guidelines specified in the Time Between Chip Selects section That is there must be at least 4 bus clocks between chip ...
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Bus Arbitration and Timing SLAVE MODE TIMING When CS is low the ST-NIC becomes a bus slave The CPU can then read or write any internal registers All register accesses are byte wide The timing for register access ...
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Preliminary Electrical Characteristics Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications b Supply Voltage ( Input Voltage ( ...
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Preliminary Electrical Characteristics Preliminary DC Specifications Symbol Parameter AUI INTERFACE PINS (TX RX and Diff Output Voltage ( Diff Output Voltage Imbalance (TX OB (Note 1) V Undershoot Voltage (TX ...
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... SRD or after SRD is de-asserted Note 3 These limits include the RC delay inherent in our test method These signals typically turn off within 15 ns enabling other devices to drive these lines with no contention AC Specs DP83902A Note All Timing is Preliminary Register Read (Latched Using ADS0) Min ...
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... Note 2 These limits include the RC delay inherent in our test method These signals typically turn off within 15 ns enabling other devices to drive these lines with no contention Note 3 CS may be asserted before of after RA0–3 and SRD since address decode begins when ACK is asserted asserted after RA0–3 and SRD rackl is referenced from falling edge Specs DP83902A Note All Timing is Preliminary (Continued Min ...
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... Note 1 ACK is not generated until CS and SWR are low and the ST-NIC has synchronized to the register access In Dual Bus Systems additional cycles will be used for a local DMA or Remote DMA to complete Note 2 CS may be asserted before or after SWR asserted after SWR wackl is referenced from falling edge Specs DP83902A Note All Timing is Preliminary (Continued) Register Write (Latched Using ADS0) Min ...
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... Note 1 Assumes ADS0 is high when RA0–3 changing Note 2 ACK is not generated until CS and SWR are low and the ST-NIC has synchronized to the register access In Dual Bus systems additional cycles will be used for a local DMA or remote DMA to complete AC Specs DP83902A Note All Timing is Preliminary (Continued ...
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... Note 2 During remote DMA transfers only a single bus transfer is performed During local DMA operations burst mode transfers are performed Note 3 These limits include the RC delay inherent in our test method These signals typically turn off within 15 ns enabling other devices to drive these lines with no contention AC Specs DP83902A Note All Timing is Preliminary (Continued) DMA Control Bus Arbitration Min ...
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... Note 2 The rate of bus clock must be high enough to support transfers to from the FIFO at a rate greater than the serial network transfers from to the FIFO Note 3 These limits include the RC delay inherent in our test method These signals typically turn off within 15 ns enabling other devices to drive these lines with no contention AC Specs DP83902A Note All Timing is Preliminary (Continued) DMA Address Generation Min ...
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... Note 1 During a burst A8–A15 are not TRI-STATE if byte wide transfers are selected On the last transfer A8–A15 are TRI-STATE as shown above Note 2 These limits include the RC delay inherent in our test method These signals typically turn off within bch lines with no contention AC Specs DP83902A Note All Timing is Preliminary (Continued) DMA Memory Read Min ...
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... Note 1 When using byte mode transfers A8–A15 are only TRI-STATE on the last transfer waz timing is only valid for last transfer in a burst Note 2 These limits include the RC delay inherent in our test method These signals typically turn off within bch lines with no contention AC Specs DP83902A Note All Timing is Preliminary (Continued) DMA Memory Write Min ...
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... Table assumes 10 MHz network clock AC Specs DP83902A Note All Timing is Preliminary (Continued) Wait State Insertion Min 10 15 The number of allowable wait states in byte mode can be calculated using 8 tnw e W (byte mode tbsck ...
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... Port Request Low from Read Acknowledge High rakw Remote Acknowledge Read Strobe Pulse Width Note 1 Start of next transfer is dependent on where RACK is generated relative to BSCK and whether a local DMA is pending AC Specs DP83902A Note All Timing is Preliminary (Continued) Remote DMA (Read Send Command) Min 11157 – ...
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... Note 1 Start of next transfer is dependent on where RACK is generated relative to BSCK and whether or not a local DMA is pending Note 2 This is not a measured value but guaranteed by design Note 3 RACK must be high for a minimum of 7 BSCK Note 4 Assumes no local DMA interleave no CS and immediate BACK AC Specs DP83902A Note All Timing is Preliminary (Continued) Min 11157 – ...
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... Note 1 The first port request is issued in response to the remote write command It is subsequently issued on T1 clock cycles following completion of remote DMA cycles Note 2 The start of the remote DMA write following WACK is dependent on where WACK is issued relative to BSCK and whether a local DMA is pending AC Specs DP83902A Note All Timing is Preliminary (Continued) Remote DMA (Write Cycle) Min ...
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... Note 2 The slower of BSCK or TXC clocks will determine the minimum time for the RESET signal to be low e If BSCK k TXC then RESET 8 c BSCK TXC BSCK then RESET 8 c TXC AC Specs DP83902A Note All Timing is Preliminary (Continued) Min 25 12 Reset Timing Min Max 11157 – 45 Max Units ...
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... Receive End of Packet Hold Time after Logic ‘‘1’’ (Note 1) teop0 Receive End of Packet Hold Time after Logic ‘‘0’’ (Note 1) Note 1 This parameter is guaranteed by design and is not tested AC Specs DP83902A Note All Timing is Preliminary (Continued) AUI Transmit Timing (End of Packet) Min 200 ...
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... TXOd ) (Note toff Transmit Hold Time at End of Packet (TXO toffd Transmit Hold Time at End of Packet (TXOd Note 1 This parameter is guaranteed by design and is not tested AC Specs DP83902A Note All Timing is Preliminary (Continued) Link Pulse Timing Min 8 80 Parameter ) (Note (Note 1) ...
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AC Timing Test Conditions All specifications are valid only if the mandatory isolation is employed and all differential signals are taken the AUI side of the pulse transformer Input Pulse Levels (TTL CMOS) Input Rise ...
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... Physical Dimensions inches (millimeters) Plastic Chip Carrier (V) Order Number DP83902AV NS Package Number V84A 100 Pin Quad Flat Pack Order Number DP83902AVF NS Package Number VF100B 68 ...
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... Physical Dimensions inches (millimeters) (Continued) Plastic Quad Flatpack (VJG) Order Number DP83902AVJG NS Package Number VJG100A 69 ...
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... Italiano National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications Order Number DP83902AVLC NS Package Number VLC100B 2 A critical component is any component of a life ...