ATMEGA324PV-10AU Atmel, ATMEGA324PV-10AU Datasheet - Page 132

• Manufacturer Part Number: ATMEGA324PV-10AU
• Description: IC MCU AVR 32K FLASH 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA324PV-10AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire/JTAG/SPI/USART
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 44TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 10 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 10MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.11 Register Description
13.11.1
8011O–AVR–07/10
TCCR1A – Timer/Counter1 Control Register A
Figure 13-13. Timer/Counter Timing Diagram, with Prescaler (f
• Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A
• Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B
The COMnA1:0 and COMnB1:0 control the Output Compare pins (OCnA and OCnB respec-
tively) behavior. If one or both of the COMnA1:0 bits are written to one, the OCnA output
overrides the normal port functionality of the I/O pin it is connected to. If one or both of the
COMnB1:0 bit are written to one, the OCnB output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-
ing to the OCnA or OCnB pin must be set in order to enable the output driver.
When the OCnA or OCnB is connected to the pin, the function of the COMnx1:0 bits is depen-
dent of the WGMn3:0 bits setting.
when the WGMn3:0 bits are set to a Normal or a CTC mode (non-PWM).
Table 13-2.
Bit
(0x80)
Read/Write
Initial Value
COMnA1/COMnB1
and ICF n
(PC and PFC PWM)
TOVn
(CTC and FPWM)
(Update at TOP)
0
0
1
1
TCNTn
TCNTn
OCRnx
(clk
as TOP)
clk
clk
I/O
(FPWM)
I/O
Tn
/8)
(if used
COM1A1
Compare Output Mode, non-PWM
R/W
7
0
COM1A0
COMnA0/COMnB0
R/W
6
0
TOP - 1
TOP - 1
Old OCRnx Value
0
1
0
1
COM1B1
Table 13-2 on page 132
R/W
5
0
COM1B0
R/W
4
0
Description
Normal port operation, OCnA/OCnB disconnected.
Toggle OCnA/OCnB on Compare Match.
Clear OCnA/OCnB on Compare Match (Set output to
low level).
Set OCnA/OCnB on Compare Match (Set output to
high level).
TOP
TOP
ATmega164P/324P/644P
R
3
–
0
shows the COMnx1:0 bit functionality
BOTTOM
TOP - 1
clk_I/O
R
2
–
0
New OCRnx Value
/8)
WGM11
R/W
1
0
BOTTOM + 1
TOP - 2
WGM10
R/W
0
0
TCCR1A
132