ATMEGA324PV-10AU Atmel, ATMEGA324PV-10AU Datasheet - Page 435

• Manufacturer Part Number: ATMEGA324PV-10AU
• Description: IC MCU AVR 32K FLASH 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA324PV-10AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire/JTAG/SPI/USART
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 44TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 10 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 10MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8011O–AVR–07/10
18 2-wire Serial Interface .......................................................................... 207
19 AC - Analog Comparator ..................................................................... 237
20 ADC - Analog-to-digital Converter ..................................................... 240
21 JTAG Interface and On-chip Debug System ..................................... 260
18.1 Features .............................................................................................................207
18.2 2-wire Serial Interface Bus Definition .................................................................207
18.3 Data Transfer and Frame Format .......................................................................208
18.4 Multi-master Bus Systems, Arbitration and Synchronization ..............................211
18.5 Overview of the TWI Module ..............................................................................213
18.6 Using the TWI .....................................................................................................215
18.7 Transmission Modes ..........................................................................................218
18.8 Multi-master Systems and Arbitration .................................................................231
18.9 Register Description ...........................................................................................232
19.1 Overview ............................................................................................................237
19.2 Analog Comparator Multiplexed Input ................................................................237
19.3 Register Description ...........................................................................................238
20.1 Features .............................................................................................................240
20.2 Overview ............................................................................................................240
20.3 Operation ............................................................................................................241
20.4 Starting a Conversion .........................................................................................242
20.5 Prescaling and Conversion Timing .....................................................................243
20.6 Changing Channel or Reference Selection ........................................................246
20.7 ADC Noise Canceler ..........................................................................................248
20.8 ADC Conversion Result .....................................................................................253
20.9 Register Description ...........................................................................................255
21.1 Features .............................................................................................................260
21.2 Overview ............................................................................................................260
21.3 TAP – Test Access Port .....................................................................................260
21.4 TAP Controller ....................................................................................................262
21.5 Using the Boundary-scan Chain .........................................................................263
21.6 Using the On-chip Debug System ......................................................................263
21.7 On-chip Debug Specific JTAG Instructions ........................................................264
21.8 Using the JTAG Programming Capabilities ........................................................264
21.9 Bibliography ........................................................................................................265
21.10 Register Description .........................................................................................265
ATmega164P/324P/644P
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