ATMEGA324PV-10AU Atmel, ATMEGA324PV-10AU Datasheet - Page 307

• Manufacturer Part Number: ATMEGA324PV-10AU
• Description: IC MCU AVR 32K FLASH 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA324PV-10AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire/JTAG/SPI/USART
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 44TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 10 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 10MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8011O–AVR–07/10
Figure 24-7. Parallel Programming Timing, Including some General Timing Requirements
Figure 24-8. Parallel Programming Timing, Loading Sequence with Timing Requirements
Note:
Figure 24-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with
Note:
(DATA, XA0/1, BS1, BS2)
1. The timing requirements shown in
1. The timing requirements shown in
XTAL1
DATA
PAGEL
XTAL1
BS1
XA0
XA1
DATA
OE
also apply to loading operation.
also apply to reading operation.
BS1
XA0
XA1
Data & Contol
Timing Requirements
RDY/BSY
PAGEL
XTAL1
ADDR0 (Low Byte)
LOAD ADDRESS
ADDR0 (Low Byte)
LOAD ADDRESS
WR
(LOW BYTE)
(LOW BYTE)
t
XLOL
t
OLDV
t
t
BVPH
DVXH
(1)
LOAD DATA
(LOW BYTE)
DATA (Low Byte)
t
t
XHXL
PHPL
(LOW BYTE)
DATA (Low Byte)
Figure 24-7 on page 307
READ DATA
Table 24-7 on page 307
t
t
t
t
t
XLXH
XLDX
XLWL
PLBX
PLWL
ATmega164P/324P/644P
t
BVDV
t
(HIGH BYTE)
LOAD DATA
BVWL
DATA (High Byte)
(HIGH BYTE)
READ DATA
DATA (High Byte)
t
XLPH
t
WLWH
LOAD DATA
WLRL
(that is, t
(that is, t
t
OHDZ
t
PLXH
t
WLBX
DVXH
DVXH
LOAD ADDRESS
LOAD ADDRESS
(LOW BYTE)
(LOW BYTE)
ADDR1 (Low Byte)
ADDR1 (Low Byte)
, t
, t
XHXL
XHXL
, and t
, and t
t
WLRH
XLDX
XLDX
(1)
307
)
)