ATMEGA324PV-10AU Atmel, ATMEGA324PV-10AU Datasheet - Page 179

• Manufacturer Part Number: ATMEGA324PV-10AU
• Description: IC MCU AVR 32K FLASH 44-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA324PV-10AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire/JTAG/SPI/USART
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Package: 44TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 10 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Controller Family/series: AVR MEGA
• No. Of I/o's: 32
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 10MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.7.3
8011O–AVR–07/10
Transmitter Flags and Interrupts
Notes:
The ninth bit can be used for indicating an address frame when using multi processor communi-
cation mode or for other protocol handling as for example synchronization.
The USART Transmitter has two flags that indicate its state: USART Data Register Empty
(UDREn) and Transmit Complete (TXCn). Both flags can be used for generating interrupts.
The Data Register Empty (UDREn) Flag indicates whether the transmit buffer is ready to receive
new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer
contains data to be transmitted that has not yet been moved into the Shift Register. For compat-
ibility with future devices, always write this bit to zero when writing the UCSRnA Register.
When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRnB is written to one, the
USART Data Register Empty Interrupt will be executed as long as UDREn is set (provided that
global interrupts are enabled). UDREn is cleared by writing UDRn. When interrupt-driven data
Assembly Code Example
C Code Example
USART_Transmit:
void USART_Transmit( unsigned int data )
{
}
; Wait for empty transmit buffer
sbis UCSRnA,UDREn
rjmp USART_Transmit
; Copy 9th bit from r17 to TXB8
cbi
sbrc r17,0
sbi
; Put LSB data (r16) into buffer, sends the data
out
ret
/* Wait for empty transmit buffer */
while ( !( UCSRnA & (1<<UDREn))) )
/* Copy 9th bit to TXB8 */
UCSRnB &= ~(1<<TXB8);
if ( data & 0x0100 )
/* Put data into buffer, sends the data */
UDRn = data;
1. These transmit functions are written to be general functions. They can be optimized if the con-
2. See “About Code Examples” on page 8.
UCSRnB |= (1<<TXB8);
tents of the UCSRnB is static. For example, only the TXB8 bit of the UCSRnB Register is used
after initialization.
UCSRnB,TXB8
UCSRnB,TXB8
UDRn,r16
;
(1)(2)
(1)(2)
ATmega164P/324P/644P
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