AT91SAM9RL64-CU Atmel, AT91SAM9RL64-CU Datasheet - Page 21

• Manufacturer Part Number: AT91SAM9RL64-CU
• Description: IC ARM9 MCU 217-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9RL64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 118
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 118
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM9RL-EK - KIT EVAL FOR AT91SAM9RLAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.6
7.7
6289C–ATARM–28-May-09
DMA Controller
Debug and Test Features
• Acting as one Matrix Master
• Embeds 2 channels
• 16 bytes/FIFO for Channel Buffering
• Linked List support with Status Write Back operation at End of Transfer
• Word, Half-word, Byte transfer support
• ARM926 Real-time In-circuit Emulator
• Debug Unit
• IEEE1149.1 JTAG Boundary-scan on All Digital Pins
a. TWI0 Transmit Channel
b. DBGU Transmit Channel
c. USART3 Transmit Channel
d. USART2 Transmit Channel
e. USART1 Transmit Channel
f.
g. AC97 Transmit Channel
h. SPI Transmit Channel
i.
j.
k. TWI0 Receive Channel
l.
m. ADC Receive Channel
n. USART3 Receive Channel
o. USART2 Receive Channel
p. USART1 Receive Channel
q. USART0 Receive Channel
r.
s. SPI Receive Channel
t.
u. SSC0 Transmit Channel
v. MCI Receive/Transmit Channel
– Two real-time Watchpoint Units
– Two Independent Registers: Debug Control Register and Debug Status Register
– Test Access Port Accessible through JTAG Protocol
– Debug Communications Channel
– Two-pin UART
– Debug Communication Channel Interrupt Handling
– Chip ID Register
USART0 Transmit Channel
SSC1 Transmit Channel
SSC0 Transmit Channel
DBGU Receive Channel
AC97 Receive Channel
SSC1 Receive Channel
AT91SAM9R64/RL64 Preliminary
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