AT91SAM9RL64-CU Atmel, AT91SAM9RL64-CU Datasheet - Page 888

• Manufacturer Part Number: AT91SAM9RL64-CU
• Description: IC ARM9 MCU 217-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9RL64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 118
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 118
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM9RL-EK - KIT EVAL FOR AT91SAM9RLAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

47.2.10
47.2.10.1
47.2.11
47.2.11.1
47.2.12
47.2.12.1
47.2.12.2
888
AT91SAM9R64/RL64 Preliminary
System Controller
TSADCC
USART
Possible event loss when reading RTT_SR
TSADCC: Multiple PENCNT detections without NOCNT
USART: RXBREAK problem when no timeguard
USART: DCD is active High instead of Low
If an event (RTTINC or ALMS) occurs within the same slow clock cycle the RTT_SR is read, the
corresponding bit might be cleared. This might lead in the loss of this event.
The software must handle RTT event as interrupt and should not poll RTT_SR.
In addition to the "Pen Contact" bit (PENCNT), the TSADCC provides a "No Contact" bit
(NOCNT) in its Status Register. When a contact loss is detected by the analog block of the
peripheral, an internal debouncer is started. However, if the contact loss is not validated by the
debouncer (e.g. if it was a glitch), the PENCNT flag is incorrectly set again in the Status Regis-
ter. This results in the PENCNT flag being set multiple times before NOCNT is set.
The user must disregard the value of the PENCNT flag after it has been set once and before the
NOCNT flag has been set. When using interrupts, the interrupt on PENCNT must be disabled
after it has occurred once, and re-enabled when NOCNT occurs.
The RXBREAK flag is not correctly handled (FRAME ERROR is set instead) when the time-
guard is 0 and the break character is located just after STOP BIT.
If the NBSTOP = 1, => TIMEGUARD should be different from 0.
SYNCHRONOUS mode is not affected, only ASYNCHRONOUS.
DCD signal is active at high level in the USART block (Modem Mode).
DCD should be active at low level.
Add an inverter.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
6289C–ATARM–28-May-09