AT91SAM9RL64-CU Atmel, AT91SAM9RL64-CU Datasheet - Page 833
![IC ARM9 MCU 217-LFBGA](/photos/12/13/121366/217-lfbga_sml.jpg)
AT91SAM9RL64-CU
Manufacturer Part Number
AT91SAM9RL64-CU
Description
IC ARM9 MCU 217-LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9RL64-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, LCD, POR, PWM, WDT
Number Of I /o
118
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
72K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
2-Wire, SPI, SSC, USART
Maximum Clock Frequency
240 MHz
Number Of Programmable I/os
118
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Controller Family/series
AT91SAM9xxx
No. Of I/o's
118
Ram Memory Size
64KB
Cpu Speed
240MHz
No. Of Timers
1
Rohs Compliant
Yes
Package
217LFBGA
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
240 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
AT91SAM9RL-EK - KIT EVAL FOR AT91SAM9RLAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9RL64-CU
Manufacturer:
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Quantity:
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Company:
Part Number:
AT91SAM9RL64-CU
Manufacturer:
ATMEL
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Part Number:
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Figure 43-5. EOCx and DRDY Flag Behavior
Figure 43-6. GOVRE and OVREx Flag Behavior
6289C–ATARM–28-May-09
(ADC_CHSR)
(ADC_CHSR)
ADC_LCDR
ADC_CDR0
ADC_CDR1
(ADC_SR)
(ADC_SR)
(ADC_SR)
(ADC_SR)
(ADC_SR)
GOVRE
ADTRG
DRDY
OVRE0
EOC0
EOC1
CH0
CH1
(ADC_CHSR)
(ADC_SR)
(ADC_SR)
EOCx
DRDY
If the
converted, the corresponding Overrun Error (OVRE) flag is set in the
Register”.
In the same way, new data converted when DRDY is high sets the bit GOVRE (General Overrun
Error) in the
The OVRE and GOVRE flags are automatically cleared when the
read.
CHx
Undefined Data
Undefined Data
“TSADCC Channel Data Register x (x = 0..5)”
Write the ADC_CR
with START = 1
SHTIM
SHTIM
Undefined Data
“TSADCC Status
Conversion
Conversion
Time
SHTIM
Read the ADC_CDRx
Data A
Conversion
Register”.
AT91SAM9R64/RL64 Preliminary
Data A
Data B
SHTIM
Write the ADC_CR
with START = 1
SHTIM
Conversion
is not read before further incoming data is
Conversion
Data B
Time
Read the ADC_LCDR
Data C
Read ADC_CDR1
Data C
“TSADCC Status
Read ADC_SR
Read ADC_CDR0
“TSADCC Status
Register”is
833
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