AT91SAM9RL64-CU Atmel, AT91SAM9RL64-CU Datasheet - Page 736
![IC ARM9 MCU 217-LFBGA](/photos/12/13/121366/217-lfbga_sml.jpg)
AT91SAM9RL64-CU
Manufacturer Part Number
AT91SAM9RL64-CU
Description
IC ARM9 MCU 217-LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9RL64-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, LCD, POR, PWM, WDT
Number Of I /o
118
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
72K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
2-Wire, SPI, SSC, USART
Maximum Clock Frequency
240 MHz
Number Of Programmable I/os
118
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Controller Family/series
AT91SAM9xxx
No. Of I/o's
118
Ram Memory Size
64KB
Cpu Speed
240MHz
No. Of Timers
1
Rohs Compliant
Yes
Package
217LFBGA
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
240 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
AT91SAM9RL-EK - KIT EVAL FOR AT91SAM9RLAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9RL64-CU
Manufacturer:
ATMEL
Quantity:
16
Company:
Part Number:
AT91SAM9RL64-CU
Manufacturer:
ATMEL
Quantity:
255
Part Number:
AT91SAM9RL64-CU
Manufacturer:
ATMEGL
Quantity:
20 000
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Table 41-2.
41.4.3
Table 41-3.
Notes:
41.4.4
736
Transfer
Control
Isochronous
Interrupt
Bulk
CONTROL
(bidirectional)
IN
(device toward host)
OUT
(host toward device)
1. Control transfer must use endpoints with one bank and can be aborted using a stall handshake.
2. Isochronous transfers must use endpoints configured with two or three banks.
AT91SAM9R64/RL64 Preliminary
USB Transfer Event Definitions
USB V2.0 High Speed BUS Transactions
USB Communication Flow
USB Transfer Events
Control Transfers
Bulk IN Transfer
Interrupt IN Transfer
Isochronous IN Transfer
Bulk OUT Transfer
Interrupt OUT Transfer
Isochronous OUT Transfer
A transfer is composed of one or several transactions;
An endpoint handles all transactions related to the type of transfer for which it has been
configured.
Each transfer results in one or more transactions over the USB bus.
There are five kinds of transactions flowing across the bus in packets:
Unidirectional
Unidirectional
Unidirectional
Bidirectional
1. Setup Transaction
2. Data IN Transaction
3. Data OUT Transaction
4. Status IN Transaction
5. Status OUT Transaction
Direction
(1)
(2)
(2)
Not guaranteed
Not guaranteed
Not guaranteed
Guaranteed
Bandwidth
• Setup transaction → Data IN transactions → Status OUT transaction
• Setup transaction → Data OUT transactions → Status IN transaction
• Setup transaction → Status IN transaction
• Data IN transaction → Data IN transaction
• Data IN transaction → Data IN transaction
• Data IN transaction → Data IN transaction
• Data OUT transaction → Data OUT transaction
• Data OUT transaction → Data OUT transaction
• Data OUT transaction → Data OUT transaction
Endpoint Size
8,16,32,64
8-1024
8-1024
8-512
Error Detection
Yes
Yes
Yes
Yes
6289C–ATARM–28-May-09
Automatic
Retrying
Yes
Yes
No
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