AT91SAM9RL64-CU Atmel, AT91SAM9RL64-CU Datasheet - Page 788
![IC ARM9 MCU 217-LFBGA](/photos/12/13/121366/217-lfbga_sml.jpg)
AT91SAM9RL64-CU
Manufacturer Part Number
AT91SAM9RL64-CU
Description
IC ARM9 MCU 217-LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9RL64-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, LCD, POR, PWM, WDT
Number Of I /o
118
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
72K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
2-Wire, SPI, SSC, USART
Maximum Clock Frequency
240 MHz
Number Of Programmable I/os
118
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Controller Family/series
AT91SAM9xxx
No. Of I/o's
118
Ram Memory Size
64KB
Cpu Speed
240MHz
No. Of Timers
1
Rohs Compliant
Yes
Package
217LFBGA
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
240 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
AT91SAM9RL-EK - KIT EVAL FOR AT91SAM9RLAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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If the exception raised is not associated to a new system bank packet (NAK_IN, NAK_OUT, ERR_FL_ISO...), then the
request cancellation may happen at any time and may immediately stop the current DMA transfer.
This may be used, for example, to identify or prevent an erroneous packet to be transferred into a buffer or to complete a
DMA buffer by software after reception of a short packet, or to perform buffer truncation on ERR_FL_ISO interrupt for
adaptive rate.
• NYET_DIS: NYET Disable (Only for High Speed Bulk OUT endpoints)
0 = If clear, this bit lets the hardware handle the handshake response for the High Speed Bulk OUT transfer.
1 = If set, this bit forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response.
Note:
• DATAX_RX: DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
0 = no effect.
1 = send an interrupt when a DATA2, DATA1 or DATA0 packet has been received meaning the whole microframe data
payload has been received.
• MDATA_RX: MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints)
0 = no effect.
1 = send an interrupt when an MDATA packet has been received and so at least one packet of the microframe data pay-
load has been received.
• ERR_OVFLW: Overflow Error Interrupt Enabled
0 = Overflow Error Interrupt is masked.
1 = Overflow Error Interrupt is enabled.
• RX_BK_RDY: Received OUT Data Interrupt Enabled
0 = Received OUT Data Interrupt is masked.
1 = Received OUT Data Interrupt is enabled.
• TX_COMPLT: Transmitted IN Data Complete Interrupt Enabled
0 = Transmitted IN Data Complete Interrupt is masked.
1 = Transmitted IN Data Complete Interrupt is enabled.
• TX_PK_RDY/ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Enabled
0 = TX Packet Ready/Transaction Error Interrupt is masked.
1 = TX Packet Ready/Transaction Error Interrupt is enabled.
• RX_SETUP/ERR_FL_ISO: Received SETUP/Error Flow Interrupt Enabled
0 = Received SETUP/Error Flow Interrupt is masked.
1 = Received SETUP/Error Flow Interrupt is enabled.
788
Caution: Interrupt source is active as long as the corresponding UDPHS_EPTSTAx register TX_PK_RDY flag remains
low. If there are no more banks available for transmitting after the software has set UDPHS_EPTSTAx/TX_PK_RDY
for the last transmit packet, then the interrupt source remains inactive until the first bank becomes free again to transmit
at UDPHS_EPTSTAx/TX_PK_RDY hardware clear.
According to the Universal Serial Bus Specification, Rev 2.0 (8.5.1.1 NAK Responses to OUT/DATA During PING Protocol), a
NAK response to an HS Bulk OUT transfer is expected to be an unusual occurrence.
AT91SAM9R64/RL64 Preliminary
6289C–ATARM–28-May-09
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