AT91SAM9RL64-CU Atmel, AT91SAM9RL64-CU Datasheet - Page 310
![IC ARM9 MCU 217-LFBGA](/photos/12/13/121366/217-lfbga_sml.jpg)
AT91SAM9RL64-CU
Manufacturer Part Number
AT91SAM9RL64-CU
Description
IC ARM9 MCU 217-LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9RL64-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, LCD, POR, PWM, WDT
Number Of I /o
118
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
72K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
2-Wire, SPI, SSC, USART
Maximum Clock Frequency
240 MHz
Number Of Programmable I/os
118
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Controller Family/series
AT91SAM9xxx
No. Of I/o's
118
Ram Memory Size
64KB
Cpu Speed
240MHz
No. Of Timers
1
Rohs Compliant
Yes
Package
217LFBGA
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
240 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
AT91SAM9RL-EK - KIT EVAL FOR AT91SAM9RLAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Figure 29-10. Fast Forcing
29.7.5
310
AT91SAM9R64/RL64 Preliminary
Protect Mode
Source 0
Source n
_
FIQ
The Fast Forcing feature does not affect the Source 0 pending bit in the Interrupt Pending Reg-
ister (AIC_IPR).
The FIQ Vector Register (AIC_FVR) reads the contents of the Source Vector Register 0
(AIC_SVR0), whatever the source of the fast interrupt may be. The read of the FVR does not
clear the Source 0 when the fast forcing feature is used and the interrupt source should be
cleared by writing to the Interrupt Clear Command Register (AIC_ICCR).
All enabled and pending interrupt sources that have the fast forcing feature enabled and that are
programmed in edge-triggered mode must be cleared by writing to the Interrupt Clear Command
Register. In doing so, they are cleared independently and thus lost interrupts are prevented.
The read of AIC_IVR does not clear the source that has the fast forcing feature enabled.
The source 0, reserved to the fast interrupt, continues operating normally and becomes one of
the Fast Interrupt sources.
The Protect Mode permits reading the Interrupt Vector Register without performing the associ-
ated automatic operations. This is necessary when working with a debug system. When a
debugger, working either with a Debug Monitor or the ARM processor's ICE, stops the applica-
tions and updates the opened windows, it might read the AIC User Interface and thus the IVR.
This has undesirable consequences:
In either case, an End of Interrupt command is necessary to acknowledge and to restore the
context of the AIC. This operation is generally not performed by the debug system as the debug
system would become strongly intrusive and cause the application to enter an undesired state.
This is avoided by using the Protect Mode. Writing DBGM in AIC_DCR (Debug Control Register)
at 0x1 enables the Protect Mode.
When the Protect Mode is enabled, the AIC performs interrupt stacking only when a write access
is performed on the AIC_IVR. Therefore, the Interrupt Service Routines must write (arbitrary
data) to the AIC_IVR just after reading it. The new context of the AIC, including the value of the
• If an enabled interrupt with a higher priority than the current one is pending, it is stacked.
• If there is no enabled pending interrupt, the spurious vector is returned.
Automatic Clear
Automatic Clear
Input Stage
Input Stage
Read IVR if Source n is the current interrupt
and if Fast Forcing is disabled on Source n.
Read FVR if Fast Forcing is
disabled on Sources 1 to 31.
AIC_IPR
AIC_IPR
AIC_IMR
AIC_IMR
AIC_FFSR
Manager
Priority
nIRQ
nFIQ
6289C–ATARM–28-May-09
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