AT91SAM9RL64-CU Atmel, AT91SAM9RL64-CU Datasheet - Page 23
![IC ARM9 MCU 217-LFBGA](/photos/12/13/121366/217-lfbga_sml.jpg)
AT91SAM9RL64-CU
Manufacturer Part Number
AT91SAM9RL64-CU
Description
IC ARM9 MCU 217-LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9RL64-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, LCD, POR, PWM, WDT
Number Of I /o
118
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
72K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
2-Wire, SPI, SSC, USART
Maximum Clock Frequency
240 MHz
Number Of Programmable I/os
118
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Controller Family/series
AT91SAM9xxx
No. Of I/o's
118
Ram Memory Size
64KB
Cpu Speed
240MHz
No. Of Timers
1
Rohs Compliant
Yes
Package
217LFBGA
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
240 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
AT91SAM9RL-EK - KIT EVAL FOR AT91SAM9RLAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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8.1
8.1.1
8.1.1.1
6289C–ATARM–28-May-09
Embedded Memories
Internal Memory Mapping
Internal SRAM
A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of
the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional
features.
Decoding breaks up the 4G bytes of address space into 16 banks of 256M bytes. The banks 1 to
8 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to
EBI_NCS5. The bank 0 is reserved for the addressing of the internal memories, and a second
level of decoding provides 1M byte of internal memory area. The bank 15 is reserved for the
peripherals and provides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master
requesting such an access.
Table 8-1
status (RCBx bit) and the BMS state at reset.
Table 8-1.
Notes:
The AT91SAM9R64/RL64 product embeds a total of 64Kbyte high-speed SRAM split in 4 blocks
of 16KBytes.
After reset and until the Remap Command is performed, the SRAM is only accessible at address
0x0030 0000.
After Remap, the SRAM also becomes available at address 0x0.
This Internal SRAM can be allocated to threes areas. Its Memory Mapping is detailed in
2.
Address
0x0000 0000
• 32 KB ROM
• 64 KB Fast SRAM
• Internal SRAM A is the ARM926EJ-S Instruction TCM. The user can map this SRAM block
anywhere in the ARM926 instruction memory space using CP15 instructions and the TCR
configuration register located in the Chip Configuration User Interface. This SRAM block is
also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus
at address 0x0010 0000.
– Single Cycle Access at full bus speed
– Single Cycle Access at full bus speed
– Supports ARM926EJ-S TCM interface at full processor speed
1. x = 0 to maximum Master number.
2. EBI NCS0 is to be connected to a 16-bit non-volatile memory. The access configuration is
summarizes the Internal Memory Mapping for each Master, depending on the Remap
defined by the reset state of SMC Setup, SMC Pulse, SMC Cycle and SMC Mode CS0
registers.
Internal Memory Mapping
BMS = 1
AT91SAM9R64/RL64 Preliminary
ROM
RCBx
(1)
= 0
EBI_NCS0
BMS =0
(2)
RCBx
SRAM
(1)
= 1
Table 8-
23
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