AT91SAM9RL64-CU Atmel, AT91SAM9RL64-CU Datasheet - Page 767

• Manufacturer Part Number: AT91SAM9RL64-CU
• Description: IC ARM9 MCU 217-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9RL64-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, LCD, POR, PWM, WDT
• Number Of I /o: 118
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 72K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: 2-Wire, SPI, SSC, USART
• Maximum Clock Frequency: 240 MHz
• Number Of Programmable I/os: 118
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Controller Family/series: AT91SAM9xxx
• No. Of I/o's: 118
• Ram Memory Size: 64KB
• Cpu Speed: 240MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 240 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: AT91SAM9RL-EK - KIT EVAL FOR AT91SAM9RLAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

41.5.4
Name:
Access Type:
• SPEED: Speed Status
0 = reset by hardware when the hardware is in Full Speed mode.
1 = set by hardware when the hardware is in High Speed mode
• DET_SUSPD: Suspend Interrupt
0 = cleared by setting the DET_SUSPD bit in UDPHS_CLRINT register
1 = set by hardware when a UDPHS Suspend (Idle bus for three frame periods, a J state for 3 ms) is detected. This triggers
a UDPHS interrupt when the DET_SUSPD bit is set in UDPHS_IEN register.
• MICRO_SOF: Micro Start Of Frame Interrupt
0 = cleared by setting the MICRO_SOF bit in UDPHS_CLRINT register.
1 = set by hardware when an UDPHS micro start of frame PID (SOF) has been detected (every 125 us) or synthesized by
the macro. This triggers a UDPHS interrupt when the MICRO_SOF bit is set in UDPHS_IEN. In case of detected SOF, the
MICRO_FRAME_NUM field in UDPHS_FNUM register is incremented and the FRAME_NUMBER field doesn’t change.
Note:
• INT_SOF: Start Of Frame Interrupt
0 = cleared by setting the INT_SOF bit in UDPHS_CLRINT.
1 = set by hardware when an UDPHS Start Of Frame PID (SOF) has been detected (every 1 ms) or synthesized by the
macro. This triggers a UDPHS interrupt when the INT_SOF bit is set in UDPHS_IEN register. In case of detected SOF, in
High Speed mode, the MICRO_FRAME_NUMBER field is cleared in UDPHS_FNUM register and the FRAME_NUMBER
field is updated.
• ENDRESET: End Of Reset Interrupt
0 = cleared by setting the ENDRESET bit in UDPHS_CLRINT.
1 = set by hardware when an End Of Reset has been detected by the UDPHS controller. This triggers a UDPHS interrupt
when the ENDRESET bit is set in UDPHS_IEN.
6289C–ATARM–28-May-09
UPSTR_RES
31
23
15
–
–
–
7
The Micro Start Of Frame Interrupt (MICRO_SOF), and the Start Of Frame Interrupt (INT_SOF) are not generated at the same
time.
UDPHS Interrupt Status Register
ENDOFRSM
DMA_6
EPT_6
30
22
14
UDPHS_INTSTA
Read-only
–
6
WAKE_UP
DMA_5
EPT_5
29
21
13
–
5
ENDRESET
DMA_4
EPT_4
28
20
12
–
4
AT91SAM9R64/RL64 Preliminary
INT_SOF
DMA_3
EPT_3
27
19
11
–
3
MICRO_SOF
DMA_2
EPT_2
26
18
10
–
2
DET_SUSPD
DMA_1
EPT_1
25
17
–
9
1
SPEED
EPT_0
24
16
–
–
8
0
767