AT91SAM9RL64-CU Atmel, AT91SAM9RL64-CU Datasheet - Page 465
![IC ARM9 MCU 217-LFBGA](/photos/12/13/121366/217-lfbga_sml.jpg)
AT91SAM9RL64-CU
Manufacturer Part Number
AT91SAM9RL64-CU
Description
IC ARM9 MCU 217-LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9RL64-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
240MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, LCD, POR, PWM, WDT
Number Of I /o
118
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
72K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
2-Wire, SPI, SSC, USART
Maximum Clock Frequency
240 MHz
Number Of Programmable I/os
118
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Controller Family/series
AT91SAM9xxx
No. Of I/o's
118
Ram Memory Size
64KB
Cpu Speed
240MHz
No. Of Timers
1
Rohs Compliant
Yes
Package
217LFBGA
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
240 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
AT91SAM9RL-EK - KIT EVAL FOR AT91SAM9RLAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Price
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Figure 34-26. Break Transmission
34.6.3.14
34.6.3.15
6289C–ATARM–28-May-09
Baud Rate
TXEMPTY
US_CR
TXRDY
Clock
Write
TXD
Receive Break
Hardware Handshaking
Start
Bit
D0
D1
D2
STTBRK = 1
The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK
commands are taken into account only if the TXRDY bit in US_CSR is at 1 and the start of the
break condition clears the TXRDY and TXEMPTY bits as if a character is processed.
Writing US_CR with the both STTBRK and STPBRK bits at 1 can lead to an unpredictable
result. All STPBRK commands requested without a previous STTBRK command are ignored. A
byte written into the Transmit Holding Register while a break is pending, but not started, is
ignored.
After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times.
Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the
start of the next character. If the timeguard is programmed with a value higher than 12, the TXD
line is held high for the timeguard period.
After holding the TXD line for this period, the transmitter resumes normal operations.
Figure 34-26
commands on the TXD line.
The receiver detects a break condition when all data, parity and stop bits are low. This corre-
sponds to detecting a framing error with data at 0x00, but FRAME remains low.
When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may
be cleared by writing the Control Register (US_CR) with the bit RSTSTA at 1.
An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchro-
nous operating mode or one sample at high level in synchronous operating mode. The end of
break detection also asserts the RXBRK bit.
The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins
are used to connect with the remote device, as shown in
D3
D4
D5
D6
D7
illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK)
Parity
Bit
Stop
Bit
Break Transmission
STPBRK = 1
AT91SAM9R64/RL64 Preliminary
Figure
34-27.
End of Break
465
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