PXAS37KBA,512 NXP Semiconductors, PXAS37KBA,512 Datasheet - Page 28

IC XA MCU 16BIT 32K OTP 68-PLCC

PXAS37KBA,512

Manufacturer Part Number
PXAS37KBA,512
Description
IC XA MCU 16BIT 32K OTP 68-PLCC
Manufacturer
NXP Semiconductors
Series
XAr
Datasheet

Specifications of PXAS37KBA,512

Core Processor
XA
Core Size
16-Bit
Speed
30MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
Processor Series
PXAS3x
Core
80C51
Data Bus Width
16 bit
Data Ram Size
1 KB
Interface Type
I2C, UART
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
50
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
568-3536-5
935262377512
PXAS37KBA

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following each write to SnBUF. This clears the interrupt flag that would
Philips Semiconductors
Serial Port Control Register
The serial port control and status register is the Special Function
Register SnCON, shown in Figure 21. This register contains not only
the mode selection bits, but also the 9th data bit for transmit and
receive (TB8_n and RB8_n), and the serial port interrupt bits (TI_n
and RI_n).
TI Flag
In order to allow easy use of the double buffered UART transmitter
feature, the TI_n flag is set by the UART hardware under two
conditions. The first condition is the completion of any byte
transmission. This occurs at the end of the stop bit in modes 1, 2, or
3, or at the end of the eighth data bit in mode 0. The second
condition is when SnBUF is written while the UART transmitter is
idle. In this case, the TI_n flag is set in order to indicate that the
second UART transmitter buffer is still available.
Typically, UART transmitters generate one interrupt per byte
transmitted. In the case of the XA UART, one additional interrupt is
generated as defined by the stated conditions for setting the TI_n
flag. This additional interrupt does not occur if double buffering is
bypassed as explained below. Note that if a character oriented
approach is used to transmit data through the UART, there could be
a second interrupt for each character transmitted, depending on the
timing of the writes to SBUF. For this reason, it is generally better to
bypass double buffering when the UART transmitter is used in
character oriented mode. This is also true if the UART is polled
rather than interrupt driven, and when transmission is character
oriented rather than message or string oriented. The interrupt occurs
at the end of the last byte transmitted when the UART becomes idle.
Among other things, this allows a program to determine when a
message has been transmitted completely. The interrupt service
routine should handle this additional interrupt.
The recommended method of using the double buffering in the
application program is to have the interrupt service routine handle a
single byte for each interrupt occurrence. In this manner the program
essentially does not require any special considerations for double
buffering. Unless higher priority interrupts cause delays in the servicing
of the UART transmitter interrupt, the double buffering will result in
transmitted bytes being tightly packed with no intervening gaps.
9-bit Mode
Please note that the ninth data bit (TB8) is not double buffered. Care
must be taken to insure that the TB8 bit contains the intended data
at the point where it is transmitted. Double buffering of the UART
transmitter may be bypassed as a simple means of synchronizing
TB8 to the rest of the data stream.
Bypassing Double Buffering
The UART transmitter may be used as if it is single buffered. The
recommended UART transmitter interrupt service routine (ISR)
technique to bypass double buffering first clears the TI_n flag upon
entry into the ISR, as in standard practice. This clears the interrupt
that activated the ISR. Secondly, the TI_n flag is cleared immediately
otherwise direct the program to write to the second transmitter buffer.
If there is any possibility that a higher priority interrupt might become
active between the write to SnBUF and the clearing of the TI_n flag,
the interrupt system may have to be temporarily disabled during that
sequence by clearing, then setting the EA bit in the IEL register.
2000 Dec 01
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I
2
C, 2 UARTs, 16 MB address range
28
1.. The maximum baud rate for a UART in mode 1 or 3 is Osc/64.
2.. The lowest possible baud rate (for a given oscillator frequency
3.. The timer reload value may never be larger than the timer range.
4.. If a timer reload value calculation gives a negative or fractional
CLOCKING SCHEME/BAUD RATE GENERATION
The XA UARTS clock rates are determined by either a fixed division
(modes 0 and 2) of the oscillator clock or by the Timer 1 or Timer 2
overflow rate (modes 1 and 3).
The clock for the UARTs in XA runs at 16x the Baud rate. If the
timers are used as the source for Baud Clock, since maximum
speed of timers/Baud Clock is Osc/4, the maximum baud rate is
timer overflow divided by 16 i.e. Osc/64.
In Mode 0, it is fixed at Osc/16. In Mode 2, however, the fixed rate
is Osc/32.
Baud Rate for UART Mode 0:
Baud Rate calculation for UART Mode 1 and 3:
The timer reload value may be calculated as follows:
NOTES:
Baud Rate for UART Mode 2:
Using Timer 2 to Generate Baud Rates
Timer T2 is a 16-bit up/down counter in XA. As a baud rate
generator, timer 2 is selected as a clock source for either/both
UART0 and UART1 transmitters and/or receivers by setting TCLKn
and/or RCLKn in T2CON and T2MOD. As the baud rate generator,
T2 is incremented as Osc/N where N = 4, 16 or 64 depending on
TCLK as programmed in the SCR bits PT1, and PTO. So, if T2 is
the source of one UART, the other UART could be clocked by either
T1 overflow or fixed clock, and the UARTs could run independently
with different baud rates.
Prescaler Select for Timer Clock (TCLK)
Pre-scaler
for all Timers T0 1 2
for all Timers T0,1,2
controlled by PT1, PT0
controlled by PT1, PT0
bits in SCR
T2MOD
T2CON
and N value) may be found by using a timer reload value of 0.
result, the baud rate requested is not possible at the given
oscillator frequency and N value.
0x418
0x419
0x440
SCR
Baud_Rate = Osc/16
Baud_Rate = Timer_Rate/16
Timer_Rate = Osc/(N*(Timer_Range– Timer_Reload_Value))
where N = the TCLK prescaler value: 4, 16, or 64.
and Timer_Range = 256 for timer 1 in mode 2.
Timer_Reload_Value = Timer_Range–(Osc/(Baud_Rate*N*16))
Baud_Rate = Osc/32
65536 for timer 1 in mode 0 and timer 2
in count up mode.
00
01
10
11
RCLK0
RCLK1
PT1
bit5
bit5
bit3
Preliminary specification
TCLK0
TCLK1
Osc/4
Osc/16
Osc/64
reserved
PT0
bit4
bit4
bit2
XA-S3