PXAS37KBA,512 NXP Semiconductors, PXAS37KBA,512 Datasheet - Page 31

IC XA MCU 16BIT 32K OTP 68-PLCC

PXAS37KBA,512

Manufacturer Part Number
PXAS37KBA,512
Description
IC XA MCU 16BIT 32K OTP 68-PLCC
Manufacturer
NXP Semiconductors
Series
XAr
Datasheet

Specifications of PXAS37KBA,512

Core Processor
XA
Core Size
16-Bit
Speed
30MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
Processor Series
PXAS3x
Core
80C51
Data Bus Width
16 bit
Data Ram Size
1 KB
Interface Type
I2C, UART
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
50
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
568-3536-5
935262377512
PXAS37KBA

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Manufacturer
Quantity
Price
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Philips Semiconductors
Clocking / Baud Rate Generation
Same as for the XA-G3.
I/O Port Output Configuration
Port output configurations are the same as for the XA-G3: open
drain, quasi-bidirectional, push-pull, and off.
External Bus
The external bus operates in the same manner as the XA-G3, but
all 24 address lines are brought out to the outside world. This
allows for a maximum of 16 Mbytes of code memory and 16
Mbytes of data memory.
Clock Output
The CLKOUT pin allows easier external bus interfacing in some
situations. This output reflects the X1 clock input to the XA, but is
delayed to match the external bus outputs and strobes. The default
is for CLKOUT to be on at reset, but it may be turned off via the
CLKD bit that has been added to the BCR register.
Reset
Active low reset input, the same as the XA-G3.
The associated RSTOUT pin provides an external indication via an
active low open drain output when an internal reset occurs. The
RSTOUT pin will be driven low when the RST pin is driven low,
when a Watchdog reset occurs or the RESET instruction is
executed. This signal may be used to inform other devices in a
system that the XA-S3 has been reset.
2000 Dec 01
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I
2
C, 2 UARTs, 16 MB address range
Figure 23. UART Multiprocessor Communication, Automatic Address Recognition
START
BIT
IN UART MODE 2 OR MODE 3 AND SM2 = 1:
– WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES
– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.
D0
INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS”
RECEIVED ADDRESS D0 TO D7
PROGRAMMED ADDRESS
D0
D1
D1
Figure 22. UART Framing Error Detection
D2
SM0_n
D2
1
1
D3
SM1_n
D3
DATA BYTE
1
0
D4
31
FEn
SM2_n
D4
reflects ALL reset sources, it cannot simply be fed back into the RST
The latched values of EA and BUSW are NOT automatically
updated when an internal reset occurs. RSTOUT may be used to
apply an external reset to the XA-S3 in order to update the
previously latched EA and BUSW values. However, since RSTOUT
pin without other logic.
The reset source identification register (RSTSRC) indicates the cause
of the most recent XA reset. The cause may have been an externally
applied reset signal, execution of the RESET instruction, or a
Watchdog reset. Figure 24 shows the fields in the RSTSRC register.
Power Reduction Modes
The XA-S3 supports Idle and Power Down modes of power
reduction. The idle mode leaves some peripherals running in order
to allow them to activate the processor when an interrupt is
generated. The power down mode stops the oscillator in order to
absolutely minimize power. The processor can be made to exit
power down mode via a reset or one of the external interrupt inputs
(INT0 or INT1). This will occur if the interrupt is enabled and its
priority is higher than that defined by IM3 through IM0. In power
down mode, the power supply voltage may be reduced to the RAM
keep-alive voltage V
contents at the point where power down mode was entered. V
must be raised to within the operating range before power down
mode is exited.
COMPARATOR
D5
1
D5
REN_n
BRn
1
D6
D6
TB8_n
OEn
D7
X
RAM
. This retains the RAM, register, and SFR
D7
STINTn
RB8_n
D8
MODE 2, 3
ONLY IN
D8
SnSTAT
TI_n
if 0, sets FE
STOP
BIT
Preliminary specification
RI_n
SU00598
SU00613
SnCON
XA-S3
DD