PXAS37KBA,512 NXP Semiconductors, PXAS37KBA,512 Datasheet - Page 41

IC XA MCU 16BIT 32K OTP 68-PLCC

PXAS37KBA,512

Manufacturer Part Number
PXAS37KBA,512
Description
IC XA MCU 16BIT 32K OTP 68-PLCC
Manufacturer
NXP Semiconductors
Series
XAr
Datasheet

Specifications of PXAS37KBA,512

Core Processor
XA
Core Size
16-Bit
Speed
30MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
Processor Series
PXAS3x
Core
80C51
Data Bus Width
16 bit
Data Ram Size
1 KB
Interface Type
I2C, UART
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
50
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
568-3536-5
935262377512
PXAS37KBA

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Manufacturer
Quantity
Price
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Manufacturer:
NXP Semiconductors
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1. Load capacitance for all outputs = 50 pF.
2. Variables V1 through V13 reflect programmable bus timing, which is programmed via the Bus Timing registers (BTRH and BTRL). Refer to
Philips Semiconductors
AC ELECTRICAL CHARACTERISTICS (3 V RANGE) (continued)
This set of parameters is referenced to the XA-S3 clock output.
NOTES:
2000 Dec 01
Address Cycle
Code Read Cycle
Data Read Cycle
Data Write Cycle
Wait Input
SYMBOL
SYMBOL
XA 16-bit microcontroller
32 K/1 K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CHLH
CLLL
CHAV
CHAX
CHPL
CHPH
IVCH
CHIX
CHIZ
CHRL
CHRH
DVCH
CHDX
CHDZ
CHWL
CHWH
QVCH
CHQX
CHWTH
the XA User Guide for details of the bus timing settings.
V1)
V2)
V3)
V4)
V5)
V6)
2
C, 2 UARTs, 16 MB address range
ALEW bit = 0, and 1.5 if the ALEW bit = 1.
ALEW bits in the BTRL register.
– For a bus cycle with no ALE, V2 = 1 if CR1/0 = 00, 2 if CR1/0 = 01, 3 if CR1/0 = 10, and 4 if CR1/0 = 11. Note that during burst
– For a bus cycle with an ALE, V2 = the total bus cycle duration (2 if CRA1/0 = 00, 3 if CRA1/0 = 01, 4 if CRA1/0 = 10, and 5 if
CRA0 bits in the BTRL register. V3 = the total bus cycle duration (2 if CRA1/0 = 00, 3 if CRA1/0 = 01, 4 if CRA1/0 = 10, and
5 if CRA1/0 = 11).
CR0 bits in the BTRL register. V4 = 1 if CR1/0 = 00, 2 if CR1/0 = 01, 3 if CR1/0 = 10, and 4 if CR1/0 = 11.
DR0 bits in the BTRH register. V5 = 1 if DR1/0 = 00, 2 if DR1/0 = 01, 3 if DR1/0 = 10, and 4 if DR1/0 = 11.
DRA0 bits in the BTRH register. V6 = the total bus cycle duration (2 if DRA1/0 = 00, 3 if DRA1/0 = 01, 4 if DRA1/0 = 10, and
5 if DRA1/0 = 11).
This variable represents the programmed width of the ALE pulse as determined by the ALEW bit in the BTRL register. V1 = 0.5 if the
This variable represents the programmed width of the PSEN pulse as determined by the CR1 and CR0 bits or the CRA1, CRA0, and
This variable represents the programmed length of an entire code read cycle with ALE. This time is determined by the CRA1 and
This variable represents the programmed length of an entire code read cycle with no ALE. This time is determined by the CR1 and
This variable represents the programmed length of an entire data read cycle with no ALE. This time is determined by the DR1 and
This variable represents the programmed length of an entire data read cycle with ALE. The time is determined by the DRA1 and
mode code fetches, PSEN does not exhibit transitions at the boundaries of bus cycles. V2 still applies for the purpose of
determining peripheral timing requirements.
CRA1/0 = 11) minus the number of clocks used by ALE (V1 + 0.5) = 2.
Example: if CRA1/0 = 10 and ALEW = 1, the V2 = 4 – (1.5 + 0.5) = 2.
FIGURE
FIGURE
26
26
26
26
26
26
26
26
26
28
28
28
28
28
30
30
30
30
31
CLKOUT rising edge to ALE rising edge
CLKOUT falling edge to ALE falling edge
CLKOUT rising edge to address valid
CLKOUT rising edge to address changing (hold time)
CLKOUT rising edge to PSEN asserted
CLKOUT rising edge to PSEN de-asserted
Instruction valid to CLKOUT rising edge (setup time)
CLKOUT rising edge to instruction changing (hold time)
CLKOUT rising edge to Bus 3-State (code read)
CLKOUT rising edge to RD asserted
CLKOUT rising edge to RD de-asserted
Data valid to CLKOUT rising edge (setup time)
CLKOUT rising edge to Data changing (hold time)
CLKOUT rising edge to Bus 3-State (data read)
CLKOUT falling edge to WR asserted
CLKOUT rising edge to WR de-asserted
Data valid to CLKOUT rising edge (setup time)
CLKOUT rising edge to Data changing (hold time)
WAIT valid prior to CLKOUT rising edge
PARAMETER
PARAMETER
8
41
MIN
30
28
30
2
0
0
4
0
LIMITS
MAX
t
t
C
C
15
11
29
16
15
20
16
19
16
Preliminary specification
4
–8
–8
XA-S3
UNIT
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns