EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 268
![IC ARM920T MCU 200MHZ 352-PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-IBZ
Manufacturer Part Number
EP9312-IBZ
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-IBZ
Core Size
16/32-Bit
Package / Case
352-BGA
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Controller Family/series
(ARM9)
A/d Converter
12 Bits
No. Of I/o Pins
65
Clock Frequency
200MHz
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1260
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9312-IBZ
Manufacturer:
CIRRUS
Quantity:
30
Company:
Part Number:
EP9312-IBZ
Manufacturer:
HITTITE
Quantity:
1 200
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8
8-4
Graphics Accelerator
EP93xx User’s Guide
8.3.1 Breshenham Line Draws
8.3.2 Pixel Step Line Draws
8.4 Memory Organization for Graphics Accelerator
Based on Breshenham's algorithm, this is the fastest of the two lines draws. Patterned lines
drawn are aligned to the major axis. Steps made in the major axis are made on a 4095/4096
pixel step per clock basis. This allows the algorithm to complete the line with the amount of
pixel draws in the major axis. Steps in the minor axis are made in sub pixel increments.
Patterned lines drawn in this mode are aligned to the major axis. A pattern up to 16 bits long
repeats on an interval up to 16 bits. This type of patterning is commonly used.
This is a sub-pixel accumulation line draw that will typically take longer to draw than a
Breshenham line draw. The major advantage of the pixel step line draw is that it provides
angularly corrected patterns. This means that the pattern of the line is applied along the line
at the appropriate angle. The number of algorithm iterations is calculated based on the
calculated pixel length of the line (Pythagorean theorem). A pattern up to 16 bits long repeats
on an interval up to 16 bits. In this mode, visual correctness is emphasized over
completeness. For higher definition patterns, details of the pattern may be lost.
Wide lines are not hardware accelerated, but may be generated by stepping and repeating
single pixel width lines.
If speed is critical, horizontal un-patterned lines may be drawn by single pixel deep block fills.
Table 8-1
P(x,y) is defined as a pixel at location x,y from the upper left corner of the screen.
Y-Axis
Note:Line drawing in the negative X or Y directions is not supported by the hardware.
X-Axis
shows a hypothetical 8 x 6 pixel matrix as it would appear on a display.
P(0,0)
P(0,1)
P(0,2)
P(0,3)
P(0,4)
P(0,5)
P(1,0)
P(1,1)
P(1,2)
P(1,3)
P(1,4)
P(1,5)
Copyright 2007 Cirrus Logic
P(2,0)
P(2,1)
P(2,2)
P(2,3)
P(2,4)
P(2,5)
Table 8-1. Screen Pixels
P(3,0)
P(3,1)
P(3,2)
P(3,3)
P(3,4)
P(3,5)
P(4,0)
P(4,1)
P(4,2)
P(4,3)
P(4,4)
P(4,5)
P(5,0)
P(5,1)
P(5,2)
P(5,3)
P(5,4)
P(5,5)
P(6,0)
P(6,1)
P(6,2)
P(6,3)
P(6,4)
P(6,5)
P(7,0)
P(7,1)
P(7,2)
P(7,3)
P(7,4)
P(7,5)
DS785UM1
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