EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 797
![IC ARM920T MCU 200MHZ 352-PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-IBZ
Manufacturer Part Number
EP9312-IBZ
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-IBZ
Core Size
16/32-Bit
Package / Case
352-BGA
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Controller Family/series
(ARM9)
A/d Converter
12 Bits
No. Of I/o Pins
65
Clock Frequency
200MHz
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1260
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9312-IBZ
Manufacturer:
CIRRUS
Quantity:
30
Company:
Part Number:
EP9312-IBZ
Manufacturer:
HITTITE
Quantity:
1 200
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DS785UM1
EGPIO[15:8]
IDEDA[2:0]
EGPIO[7:0]
DD[15:12]
ROW[7:0]
IDECS1n
IDECS0n
COL[7:0]
DD[11:8]
GRLED
RDLED
SLA[1:0]
DD[7:0]
EECLK
EEDAT
DIORn
4. EEDAT is the EEPROM data pin.
5. ROW[7:0] are the Key Matrix row pins.
6. COL[7:0] are the Key Matrix column pins.
1. IDEDA[2:0], IDECS0n, IDECS1n, and DIORn are IDE control pins.
2. DD[15:0] are the IDE data pins. DD[11:8] has no GPIO pin mapping.
3. GRLED is the Green LED pin.
4. RDLED is the Red LED pin.
5. EECLK is the EEPROM clock pin.
6. EEDAT is the EEPROM data pin.
7. ROW[7:0] are the Key Matrix row pins.
8. COL[7:0] are the Key Matrix column pins.
Name
Pin
1
5
6
3
4
2
2
8
1
1
7
2
1
IDEDA[2:0]
Function
ROW[7:0]
DD[15:12]
Port G3:2
IDECS1n
IDECS0n
COL[7:0]
Default
DD[11:8]
Port E0
Port E1
Port G0
Port G1
DD[7:0]
DIORn
Port A
Port B
Table 28-3. EP9312 GPIO Port to Pin Map
Function in
IDEDA[2:0]
DD[15:12]
Port G3:2
IDECS1n
IDECS0n
Copyright 2007 Cirrus Logic
DD[11:8]
Port G0
Port G1
Port E0
Port E1
DD[7:0]
GonK
DIORn
Mode
Port C
Port D
Port A
Port B
Function in
DD[15:12]
ROW[7:0]
Port G3:2
Port E7:5
EonIDE
COL[7:0]
DD[11:8]
Port G0
Port G1
DD[7:0]
Port E0
Port E1
Port E4
Port E3
Port E2
Mode
Port A
Port B
Function in
IDEDA[2:0]
ROW[7:0]
GonIDE
Port G3:2
IDECS1n
IDECS0n
Port G7:4
COL[7:0]
DD[11:8]
Port G0
Port G1
DD[7:0]
Port E0
Port E1
DIORn
Mode
Port A
Port B
Function in
IDEDA[2:0]
DD[15:12]
EP93xx User’s Guide
Port G3:2
ROW[7:0]
IDECS1n
IDECS0n
HonIDE
COL[7:0]
DD[11:8]
Port E0
Port E1
Port G0
Port G1
DIORn
Mode
Port A
Port B
Port H
GPIO Interface
28-7
28
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