EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 684
![IC ARM920T MCU 200MHZ 352-PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-IBZ
Manufacturer Part Number
EP9312-IBZ
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-IBZ
Core Size
16/32-Bit
Package / Case
352-BGA
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Controller Family/series
(ARM9)
A/d Converter
12 Bits
No. Of I/o Pins
65
Clock Frequency
200MHz
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1260
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9312-IBZ
Manufacturer:
CIRRUS
Quantity:
30
Company:
Part Number:
EP9312-IBZ
Manufacturer:
HITTITE
Quantity:
1 200
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21
21-28
I
EP93xx User’s Guide
2
S Controller
i2s_rx_bcr:
i2s_rx_nbcg:
i2s_mstr:
i2s_rrel:
i2s_rckp:
i2s_rlrs:
Copyright 2007 Cirrus Logic
RX bit clock rate.
00 - I2SRXClkCfg[4] defines the bit clock generation.
01 - Bit clock rate is fixed at 32x. Word length is ignored.
10 - Bit clock rate is fixed at 64x. Word length is ignored.
11 - Bit clock rate is fixed at 128x. Word length is ignored.
Defines RX not bit clock gating mode.
If I2SRXClkCfg[5:6] = 00, this bit defines the bit clock rate,
otherwise ignored.
Bit clock rate = 32x if word length is 16.
Bit clock rate = 64x if word length is 32.
Bit clock rate = 64x if word length is 24.
There is a special case when the word length is 24.
If this bit = 0 and the word length is 24, the last 8 cycles
are gated off in each word.
If this bit = 1 and the word length is 24, the last 8 cycles
are not gated off in each word.
Defines if the RX Audio clocks are slave or master.
0 - slave mode.
1 - master mode.
Determines the timing of the lrckr with respect to the sdix
data inputs.
0 - Transition of lrckr occurs together with the first data bit.
1 - Transition of lrckr occurs one bitclk cycle before the first
sdix data bit.
Defines polarity of the RX bitclk.
1 - Positive clock polarity. The lrckr and sdix lines change
synchronously with the positive edge of the bitclk and are
considered valid during negative transitions.
0 - Negative clock polarity. The lrckr and sdix lines change
synchronously with the negative edge of the bitclk and are
considered valid during positive transitions.
Defines the polarity or lrckr.
0 - if lrckr is low then it is the left word, if lrckr is high then it
is the right word.
1 - if lrckr is low then it is the right word, if lrckr is high then
it is the left word.
DS785UM1
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