EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 547
![IC ARM920T MCU 200MHZ 352-PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-IBZ
Manufacturer Part Number
EP9312-IBZ
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-IBZ
Core Size
16/32-Bit
Package / Case
352-BGA
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Controller Family/series
(ARM9)
A/d Converter
12 Bits
No. Of I/o Pins
65
Clock Frequency
200MHz
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1260
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9312-IBZ
Manufacturer:
CIRRUS
Quantity:
30
Company:
Part Number:
EP9312-IBZ
Manufacturer:
HITTITE
Quantity:
1 200
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UART1DMACtrl
Modem Register Descriptions
UART1ModemCtrl
DS785UM1
31
15
31
15
Address:
Default:
Definition:
Bit Descriptions:
Address:
30
14
30
14
29
13
29
13
28
12
28
12
0x808C_0028 - Read/Write
0x0000_0000
UART DMA Control Register
RSVD:
DMAERR:
TXDMAE:
RXDMAE:
0x808C_0100 - Read/Write
RSVD
27
11
27
11
26
10
26
10
Copyright 2007 Cirrus Logic
RSVD
25
25
9
9
Reserved. Unknown During Read.
RX DMA error handing enable. If 0, the RX DMA interface
ignores error conditions in the UART receive section. If 1,
the DMA interface stops and notifies the DMA block when
an error occurs. Errors include break errors, parity errors,
and framing errors.
TX DMA interface enable. Setting to 1 enables the private
DMA interface to the transmit FIFO.
RX DMA interface enable. Setting to 1 enables the private
DMA interface to the receive FIFO.
24
24
8
8
RSVD
RSVD
23
23
7
7
0
UART1 With HDLC and Modem Control Signals
22
22
6
6
0
21
21
5
5
0
LOOP
20
20
4
4
OUT2
19
19
3
3
EP93xx User’s Guide
DMAERR
OUT1
18
18
2
2
TXDMAE
RTS
17
1
17
1
RXDMAE
14-25
DTR
16
0
16
0
14
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