EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 513
![IC ARM920T MCU 200MHZ 352-PBGA](/photos/12/23/122390/mfg_ep9312_series_sml.jpg)
EP9312-IBZ
Manufacturer Part Number
EP9312-IBZ
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-IBZ
Core Size
16/32-Bit
Package / Case
352-BGA
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Controller Family/series
(ARM9)
A/d Converter
12 Bits
No. Of I/o Pins
65
Clock Frequency
200MHz
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1260
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9312-IBZ
Manufacturer:
CIRRUS
Quantity:
30
Company:
Part Number:
EP9312-IBZ
Manufacturer:
HITTITE
Quantity:
1 200
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DS785UM1
13.9 Registers
Boot Option
(ASDO)
The Synchronous Memory controller has seven registers as shown in
Configuration registers allow software to specify the operating parameters of the
Synchronous Memory controller according to the memory device types being used. The
Refresh Timer register allows software to specify the time period between successive
synchronous memory refresh commands. The Boot Status allows software to determine the
state of the boot configuration pins.
X
X
X
1
0
0x8006_000C
0x8006_001C
0x8006_0000
0x8006_0004
0x8006_0008
0x8006_0010
0x8006_0014
0x8006_0018
Address
A31
Table 13-13. Synchronous Memory Controller Registers
0
1
1
1
1
Table 13-12. Address Bits Used for Chip Select
Reserved
"GlConfig"
"RefrshTimr"
"BootSts"
"SDRAMDevCfg[3:0]"
(See Below)
SDRAMDevCfg[3:0]
SDRAMDevCfg[3:0]
SDRAMDevCfg[3:0]
SDRAMDevCfg[3:0]
Copyright 2007 Cirrus Logic
A30
0
1
1
1
1
Name
A29
0
1
1
0
0
Global Configuration
Refresh Timer
Boot Configuration Pins Status
Synchronous Device Configuration 0
Synchronous Device Configuration 1
Synchronous Device Configuration 2
Synchronous Device Configuration 3
SDRAM, SyncROM, and SyncFLASH Controller
Description
A28
0
1
0
1
0
Table
EP93xx User’s Guide
13-13. The
Chip select
nSDCS3
nSDCS3
nSDCS2
nSDCS1
nSDCS0
13-17
13
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