EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 687
EP9312-IBZ
Manufacturer Part Number
EP9312-IBZ
Description
IC ARM920T MCU 200MHZ 352-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9312-IBZ
Core Size
16/32-Bit
Package / Case
352-BGA
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Controller Family/series
(ARM9)
A/d Converter
12 Bits
No. Of I/o Pins
65
Clock Frequency
200MHz
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1260
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9312-IBZ
Manufacturer:
CIRRUS
Quantity:
30
Company:
Part Number:
EP9312-IBZ
Manufacturer:
HITTITE
Quantity:
1 200
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I2SGlCtrl
DS785UM1
31
15
Address:
Default:
Definition:
Bit Descriptions:
The I
The I
for the data registers can be written without the I
clock cycles when writing to any of the control status registers.
When the I
this register.
The I
0. This will allow data be sent in a loop fashion from the transmitter back through the receiver.
This applies to all channels, with TX1 looped to RX1, and TX2 looped to RX2. When
loopback is active, data at the receiver input is ignored and transmit data is sent out normally.
The transmit section will control the clock configuration during loopback the same as if full-
duplex operation was used.
30
14
2
2
2
S global register deals with enabling the block and whether loopback mode is used.
S enable bit determines whether the PCLK is turned on for the I
S controller loopback mode bit determines if TX channel 0 is connected to RX channel
29
13
2
S controller is required to transmit or receive data, PCLK must be turned on via
28
12
rx2_fifo_empty:
rx2_fifo_half_full: when = 1, FIFO is half full, otherwise less than half full
0x8082_000C - Read/Write
0x0000_0000
I
RSVD:
i2s_ife:
i2s_loopback:
2
S Global Control Register
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
RSVD
when = 1, FIFO is empty, otherwise not empty
Reserved. Unknown During Read.
Defines if I
for the I
0 - PCLK is off.
1 - PCLK is on.
Defines loopback operation.
0 - not in loopback mode
1 - Loopback mode selected.
24
8
RSVD
2
S controller.
23
7
2
S controller is enabled and PCLK is turned on
2
S PCLK enabled. The ARM provides its own
22
6
21
5
20
4
19
3
2
S. All registers except
18
2
EP93xx User’s Guide
i2s_loopback
17
I
1
2
S Controller
i2s_ife
21-31
16
0
21
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