DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 439

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 13 Timer Connection
13.4.2
Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation)
The timer connection and TMRX can be used to generate signals with different duty cycles and
rising/falling edges (clamp waveforms) in synchronization with the input signal (IHI signal).
Three clamp waveforms can be generated: the CL1, CL2, and CL3 signals. In addition, the CL4
signal can be generated using the TMRY. Figure 13.5 shows a block diagram for clamp waveform
generation.
The CL1 signal rises simultaneously with the rise of the IHI signal, and when the CL1 signal is
high, the CL2 signal rises simultaneously with the fall of the IHI signal. The fall of both the CL1
and CL2 signals can be specified by TCORA.
The rise of the CL3 signal can be specified as simultaneous with the sampling of the fall of the IHI
signal using the system clock, and the fall of the CL3 signal can be specified by TCORC. The CL3
signal can also fall when the IHI signal rises.
TCNT of the TMRX is set to count internal clock pulses and to be cleared on the rising edge of the
external reset signal (IHI signal).
The value to be used as the CL1 signal pulse width is written to TCORA. Write a value of H'02 or
more to TCORA when an internal clock φ is selected as the TMRX counter clock, and a value or
H'01 or more when φ/2 is selected. When an internal clock φ is selected, the CL1 signal pulse
width is (TCORA set value + 3 ± 0.5). When the CL2 signal is used, the setting must be made so
that this pulse width is greater than the IHI signal pulse width.
The value to be used as the CL3 signal pulse width is written to TCORC. TICR of the TMRX
captures the value of TCNT at the inverse of the external reset signal edge (in this case, the falling
edge of the IHI signal). The timing of the fall of the CL3 signal is determined by the sum of the
contents of TICR and TCORC. Caution is required if the rising edge of the IHI signal precedes the
fall timing set by the contents of TCORC, since the IHI signal will cause the CL3 signal to fall.
Examples of TCR settings of the TMRX are the same as those in table 13.5. The clamp waveform
timing charts are shown in figures 13.6 and 13.7.
Since the rise of the CL1 and CL2 signals is synchronized with the edge of the IHI signal, and
their fall is synchronized with the system clock, the pulse width variation is equivalent to the
resolution of the system clock.
Both the rise and the fall of the CL3 signal are synchronized with the system clock and the pulse
width is fixed, but there is a variation in the phase relationship with the IHI signal equivalent to
the resolution of the system clock.
Rev.2.00 May. 28, 2009 Page 399 of 732
REJ09B0059-0200