DF2437FV Renesas Electronics America, DF2437FV Datasheet - Page 633

• Manufacturer Part Number: DF2437FV
• Description: IC H8S/2437 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of DF2437FV

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 20.4.4, Storable Area for Procedure Program and
Program Data.
20.4.4
In the descriptions in the previous section, storable areas for the programming/erasing procedure
programs and program data are assumed to be in the on-chip RAM. However, storable areas can
be placed in other areas, such as part of flash memory which is not to be programmed or erased, or
somewhere in the external address space by using the following conditions.
(1) Conditions that Apply to Programming/Erasing
1. The on-chip programming/erasing program is downloaded from the address in the on-chip
2. The on-chip programming/erasing program will use 128 bytes at the maximum as a stack. So,
3. Download by setting the SCO bit to 1 will lead to switching of the MAT. If, therefore, this
4. The flash memory is accessible until the start of programming or erasing, that is, until the
5. The flash memory is not accessible during programming/erasing operations, therefore, the
6. After programming/erasing, an access to the flash memory is prohibited until FKEY is cleared.
7. Switching of the MATs by FMATS should be needed when programming/erasing of the user
8. When the data storable area indicated by programming parameter FMPDR is within the flash
RAM specified by FTDAR, therefore, this area is not available for use.
make sure that this area is secured.
operation is used, it should be executed from the on-chip RAM.
result of downloading has been determined. When in a mode in which the external address
space is not accessible, such as single-chip mode, the required procedure programs, NMI
handling vector, and NMI handler should be transferred to the on-chip RAM before
programming/erasing of the flash memory starts.
operation program downloaded to the on-chip RAM is executed. The NMI-handling vector and
processing programs such as that which activate the operation program, and NMI handler
should thus be stored in on-chip RAM other than flash memory or the external bus space.
The reset period (RES = 0) must be in place for more than 100 μs when the LSI mode is
changed to reset on completion of a programming/erasing operation.
Transitions to the reset state, and hardware standby mode are prohibited during
programming/erasing. When the reset signal is accidentally input to the chip, a longer period in
the reset state than usual (100 μs) is needed before the reset signal is released.
MAT is operated in user boot mode. The program which switches the MATs should be
executed in the on-chip RAM. See section 20.6, Switching between User MAT and User Boot
MAT. Please make sure you know which MAT is selected when switching between them.
memory area, an error will occur even when the data stored is normal. Therefore, the data
Storable Area for Procedure Program and Program Data
Rev.2.00 May. 28, 2009 Page 593 of 732
REJ09B0059-0200