D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 129

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Saved Status Register (SSR): The contents of SR are saved to SSR in the event of an exception
or interrupt.
Saved Program Counter (SPC): The address of an instruction at which an interrupt or exception
occurs is saved to SPC.
Global Base Register (GBR): GBR is referenced as the base address in a GBR-referencing MOV
instruction.
Vector Base Register (VBR): VBR is referenced as the branch destination base address in the
event of an exception or interrupt.
Bit
27 to 16 —
15
14 to 10 —
9
8
7
6
5
4
3, 2
1
0
Bit Name Initial Value R/W
FD
M
Q
IMASK3
IMASK2
IMASK1
IMASK0
—
S
T
All 0
0
All 0
—
—
1
1
1
1
All 0
—
—
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
FPU Disable Bit
A reset clears this bit to 0.
When this bit is set to 1 and an FPU instruction is not
in a delay slot, a general FPU disable exception
occurs. When this bit is set to 1 and an FPU
instruction is in a delay slot, a slot FPU disable
exception occurs. (FPU instructions: H’F***
instructions and LDS (.L)/STS(.L) instructions using
FPUL/FPSCR)
Reserved
These bits are always read as 0. The write value
should always be 0.
M Bit
Q Bit
Used by the DIV0S, DIV0U, and DIV1 instructions.
Interrupt Mask Level Bits
An interrupt whose priority is equal to or less than the
value of the IMASK bits is masked. These bits are not
modified by an interrupt.
Reserved
These bits are always read as 0. The write value
should always be 0.
S Bit
Used by the MAC instruction.
T Bit
Indicates true/false or carry/borrow.
Rev. 2.00 Feb. 12, 2010 Page 45 of 1330
REJ09B0554-0200