D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 771

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

19.3.14 Receive FIFO Data Count Register (ICRFDR)
ICRFDR is a 32-bit register that indicates the byte count in ICRXD. The lower 5 bits indicate the
number of receive bytes in ICRXD. ICRFDR can always be read by the CPU. H'0000 0000
indicates that ICRXD contains no receive data, while H'0000 0010 indicates that it holds 16 bytes
of receive data.
Initial value:
Initial value:
19.3.15 Transmit FIFO Data Count Register (ICTFDR)
ICTFDR is a 32-bit register that indicates the byte count stored in ICTXD. The lower 5 bits
indicates the number of transmit bytes in ICTXD. ICTFDR can always be read by the CPU.
H'0000 0000 indicates that ICTXD contains no transmit data, while H'0000 0010 indicates that it
holds 16 bytes of transmit data.
Initial value:
Initial value:
Bit
0
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
Bit Name
TXIE
31
15
31
15
R
R
R
R
0
0
0
0
-
-
-
-
30
14
30
14
R
R
R
R
-
-
-
-
0
0
0
0
29
13
29
13
R
R
R
R
0
0
0
0
-
-
-
-
Initial Value
0
28
12
28
12
R
R
R
R
0
0
0
0
-
-
-
-
27
11
27
11
R
R
R
R
0
0
0
0
-
-
-
-
R/W
R/W
26
10
26
10
R
R
R
R
-
0
-
0
-
0
-
0
25
25
R
R
R
R
-
0
9
-
0
-
0
9
-
0
Description
Transmit Interrupt Enable
Enables or disables the generation of the transmit
FIFO data empty interrupt (TXI) when serial
transmit data is transferred from ICTXD to the
shift register, the byte count in ICTXD is equal to
or smaller than the transmit trigger byte count,
and the TDFE flag of ICFSR is set to 1.
0: The transmit FIFO data empty interrupt (TXI) is
1: The transmit FIFO data empty interrupt (TXI) is
24
24
R
R
R
R
0
8
0
0
8
0
-
-
-
-
disabled
enabled
23
23
R
R
R
R
0
7
0
0
7
0
-
-
-
-
Rev. 2.00 Feb. 12, 2010 Page 687 of 1330
22
22
R
R
R
R
0
6
0
0
6
0
-
-
-
-
21
21
R
R
R
R
0
5
0
0
5
0
-
-
-
-
R4
20
20
T4
Section 19 I
R
R
R
R
0
4
0
4
0
0
-
-
19
R3
19
T3
R
R
0
3
0
R
0
3
0
R
-
-
REJ09B0554-0200
R2
18
18
T2
R
R
R
R
0
2
0
0
2
0
-
-
2
C Bus Interface
R1
17
17
T1
R
R
R
R
0
1
0
0
1
0
-
-
R0
16
16
T0
R
R
R
R
0
0
0
0
0
0
-
-