D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 148

• Manufacturer Part Number: D6417760BP200ADV
• Description: IC SUPER H MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D6417760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Workarounds
1. Use FPSCR.RM = 01, that is to say Round to Zero rather than Round to Nearest mode.
2. Use FPSCR.RM = 00, that is to say Round to Nearest mode, and set the enable field to 1 to
3.7.2
When the maximum error produced by the FIPR or FTRV instruction exceeds the maximum value
expressible as a normalized number (H'7F7FFFFF), the overflow flag may be set, even through
the operation result is a positive or negative zero (H'00000000 or H'80000000).
Example: The operation result (FR7) after executing the instruction FIPR FV4, FV0 is
H'00000000 (positive zero), but the overflow flag may be set nevertheless.
FPSCR = H'00040001
FR0 = H'FF7EF631 , FR1 = H80000000 , FR2 = H'8087F451 , FR3 = H'7F7EF631
FR4 = H'7F7EF631 , FR5 = H'0087F451 , FR6 = H'7F7EF631 , FR7 = H'7F7EF631
Workaround: Avoid using the FIPR and FTRV instructions, and use the FADD, FMUL, and
FMAC instructions instead.
Rev. 2.00 Feb. 12, 2010 Page 64 of 1330
REJ09B0554-0200
b. FPU
enable generation of inexact exceptions so that the exception handling routine can be used to
check whether or not an underflow has occurred.
Operation result: H'00100000 00000000
FPSCR: H'000C300C
Operation result: H'00100000 00000000
FPSCR: H'000C1004
Setting of Overflow Flag by FIPR or FTRV Instruction