AT90PWM81-16SF Atmel, AT90PWM81-16SF Datasheet - Page 133
AT90PWM81-16SF
Manufacturer Part Number
AT90PWM81-16SF
Description
IC MCU AVR 8K FLASH ISP 20SOIC
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM81-16MN.pdf
(325 pages)
Specifications of AT90PWM81-16SF
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
20-SOIC (7.5mm Width)
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer:
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12.24.1
12.25 PSC Register Definition
12.25.1
7734P–AVR–08/10
List of Interrupt Vector
PSC 2 Synchro and Output Configuration – PSOC2
Each PSC provides 3 interrupt vectors
See “PSC2 Interrupt Mask Register – PIM2” on page 143.
.
Registers are explained for PSC0. They are identical for PSC1. For PSC2 only different registers are
described.
Bit
Read/Write
Initial Value
• Bit 7 – POS23 : PSCOUT23 Selection (PSC2 only)
When this bit is clear, PSCOUT23 outputs the waveform generated by Waveform Generator B.
When this bit is set, PSCOUT23 outputs the waveform generated by Waveform Generator A.
• Bit 6 – POS22 : PSCOUT22 Selection (PSC2 only)
When this bit is clear, PSCOUT22 outputs the waveform generated by Waveform Generator A.
When this bit is set, PSCOUT22 outputs the waveform generated by Waveform Generator B.
• Bit 5:4 – PSYNCn1:0: Synchronization Out for ADC Selection
Select the polarity and signal source for generating a signal which will be sent to the ADC for
synchronization.
Table 12-11.
PSYNCn1
0
0
1
1
• PSCn EC (End of Cycle): When enabled and when a match with OCRnRB occurs
• PSCn EEC (End of Enhanced Cycle): When enabled and when a match with OCRnRB occurs at the
• PSCn CAPT (Capture Event): When enabled and one of the two following events occurs : retrigger,
15th enhanced cycle
capture of the PSC counter or Synchro Error.
R/W
7
POS23
0
Synchronization Source Description in One/Two/Four Ramp Modes
PSYNCn0
0
1
0
1
6
POS22
R/W
0
Description
Send signal on leading edge of PSCOUTn0 (match with OCRnSA)
Send signal on trailing edge of PSCOUTn0 (match with OCRnRA or
fault/retrigger on part A)
Send signal on leading edge of PSCOUTn1 (match with OCRnSB)
Send signal on trailing edge of PSCOUTn1 (match with OCRnRB or
fault/retrigger on part B)
5
PSYNC21
R/W
0
4
PSYNC20
R/W
0
3
POEN2D
R/W
0
2
POEN2B
R/W
0
1
POEN2C
R/W
0
AT90PWM81
0
POEN2A
R/W
0
PSOC2
133
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