AT90PWM81-16SF Atmel, AT90PWM81-16SF Datasheet - Page 188
AT90PWM81-16SF
Manufacturer Part Number
AT90PWM81-16SF
Description
IC MCU AVR 8K FLASH ISP 20SOIC
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM81-16MN.pdf
(325 pages)
Specifications of AT90PWM81-16SF
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
20-SOIC (7.5mm Width)
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Part Number:
AT90PWM81-16SF
Manufacturer:
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14.5.2
14.5.3
188
AT90PWM81
SPI Status Register – SPSR
SPI Data Register – SPDR
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in SPCR is set
and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this
will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt han-
dling vector. Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set,
then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit
(and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing
the SPI Data Register.
• Bit 5..1 – Res: Reserved Bits
These bits are reserved bits in the AT90PWM81 and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Mas-
ter mode (see
When the SPI is configured as Slave, the SPI is only guaranteed to work at f
The SPI interface on the AT90PWM81 is also used for program memory and EEPROM downloading or
uploading. See
• Bits 7:0 - SPD7:0: SPI Data
The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI
Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift
Register Receive buffer to be read.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Table
7
SPD7
R/W
X
7
SPIF
R
0
Serial Programming Algorithm261
14-5). This means that the minimum SCK period will be two CPU clock periods.
6
SPD6
R/W
X
6
WCOL
R
0
5
SPD5
R/W
X
5
–
R
0
4
SPD4
R/W
X
4
–
R
0
for serial programming and verification.
3
SPD3
R/W
X
3
–
R
0
2
SPD2
R/W
X
2
–
R
0
1
SPD1
R/W
X
1
–
R
0
clkio
/4 or lower.
0
SPD0
R/W
X
0
SPI2X
R/W
0
7734P–AVR–08/10
SPDR
Undefined
SPSR
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