AT90PWM81-16SF Atmel, AT90PWM81-16SF Datasheet - Page 77

• Manufacturer Part Number: AT90PWM81-16SF
• Description: IC MCU AVR 8K FLASH ISP 20SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM81-16SF

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (7.5mm Width)
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7734P–AVR–08/10
• ADC1/ACMP2_OUT, Bit 3
ADC1, Analog to Digital Converter, input channel 1.
ACMP2_OUT, Analog Comparator 2 Output.
• ADC0/ACMP1, Bit 2
ADC0, Analog to Digital Converter, input channel 0
ACMP1, Analog Comparator 1 Positive Input. Configure the port pin as input with the internal pull-up
switched off to avoid the digital port function from interfering with the function of the Analog
Comparator.
• PSCOUTR0/PSCINrB – Bit 1
PSCOUTR0: Output 0 of PSCR.
PCSINrB, PSCR Second Alternate Digital Input.
• ACMP3_OUT_A/SS/CLKO – Bit 0
ACMP2_OUT_A, Analog Comparator 2 Alternate Output.
SS: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an input regard-
less of the setting of DDDn. As a slave, the SPI is activated when this pin is driven low. When the SPI is
enabled as a master, the data direction of this pin is controlled by DDDn. When the pin is forced to be an
input, the pull-up can still be controlled by the PORTDn bit.
CLKO, Divided System Clock: The divided system clock can be output on this pin. The divided system
clock will be output if the CKOUT Fuse is programmed, regardless of the PORTDn and DDDn settings. It
will also be output during reset.
Table 9-7
9-5 on page
Table 9-7.
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
and
71.
Table 9-8
Overriding Signals for Alternate Functions PD7..PD4
PD7/
ADC10/ PSCINrA
relates the alternate functions of Port D to the overriding signals shown in
PD6/APM0+
.
PD5/AMP0-
/ADC7
AT90PWM81
PD4/ACMP3M/
ADC2/PSCIN2A
Figure
77