AT90PWM81-16SF Atmel, AT90PWM81-16SF Datasheet - Page 83
AT90PWM81-16SF
Manufacturer Part Number
AT90PWM81-16SF
Description
IC MCU AVR 8K FLASH ISP 20SOIC
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM81-16MN.pdf
(325 pages)
Specifications of AT90PWM81-16SF
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
20-SOIC (7.5mm Width)
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90PWM81-16SF
Manufacturer:
Atmel
Quantity:
2 428
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10.0.2
10.0.3
7734P–AVR–08/10
External Interrupt Mask Register – EIMSK
External Interrupt Flag Register – EIFR
• Bits 2..0 – INT2 – INT0: External Interrupt Request 3 - 0 Enable
When an INT2 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the cor-
responding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt
Control Register – EICRA – defines whether the external interrupt is activated on rising or falling edge or
level sensed. Activity on any of these pins will trigger an interrupt request even if the pin is enabled as an
output. This provides a way of generating a software interrupt.
• Bits 2..0 – INTF2 - INTF0: External Interrupt Flags 3 - 0
When an edge or logic change on the INT2:0 pin triggers an interrupt request, INTF2:0 becomes set (one).
If the I-bit in SREG and the corresponding interrupt enable bit, INT2:0 in EIMSK, are set (one), the MCU
will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively,
the flag can be cleared by writing a logical one to it. These flags are always cleared when INT2:0 are con-
figured as level interrupt.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
7
-
R/W
0
7
-
R/W
0
6
-
R/W
0
6
-
R/W
0
5
-
R/W
0
5
-
R/W
0
0
0
4
-
R/W
4
-
R/W
3
-
R/W
0
3
-
R/W
0
2
INT2
R/W
0
2
INTF2
R/W
0
1
INT1
R/W
0
1
INTF1
R/W
0
AT90PWM81
0
IINT0
R/W
0
0
IINTF0
R/W
0
EIMSK
EIFR
83
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